Active solid-state devices (e.g. – transistors – solid-state diode – With means to control surface effects – Insulating coating
Reexamination Certificate
1999-06-09
2001-08-14
Lee, Eddie (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
With means to control surface effects
Insulating coating
C257S759000, C257S773000, C257S774000
Reexamination Certificate
active
06274923
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to a semiconductor device, and more particularly to, a semiconductor device with a trench interconnect that is buried into an interconnect trench formed in organic insulation film, and relates to a method for making the semiconductor device.
BACKGROUND OF THE INVENTION
Along with the development in micro-structuring of semiconductor device, Cu films with a low resistivity have been used instead of Al film. Also, with the formation of multi-layer interconnects, the planarization of surface is further desired. Thus, a so-called trench interconnect formed by burying conductive film into a trench formed in interlayer insulation film has been used.
A known method for forming the trench interconnect of copper (Cu) buried into a trench that is formed in inorganic insulation film is described in S. Lakshminarayanan et al., “Dual Damascene Copper Metallization Processing Using Chemical-Mechanical Polishing”, Proceedings of 1994 VLSI Multilevel Interconnection Conference, pp. 49-55, 1994. Referring to
FIGS. 1A
to
1
F, this method is explained. First, as shown in
FIG. 1A
, first inorganic film
2
of about 2 &mgr;m thick is deposited on a silicon substrate
1
, and then a first interconnect trench
3
of about 500 nm deep is formed by dry etching.
Then, as shown in
FIG. 1B
, first Ti film
4
and first Cu film
5
are sequentially deposited by sputtering, thereby the first interconnect trench
3
is filled with.
Then, as shown in
FIG. 1C
, the first Cu film
5
is removed polishing by the CMP (chemical mechanical polishing) method, and further the first Ti film
4
is removed using diluted hydrofluoric acid. Thus, a first trench interconnect
5
a
of the first Cu film
5
and a barrier metal layer
4
a
of the first Ti film
4
are formed.
Further, though not shown, implanting boron (B) onto the surface of the first trench interconnect
5
a
, a protection layer is formed on the surface of the first trench interconnect
5
a.
Then, as shown in
FIG. 1D
, second inorganic insulation film
6
of silicon oxide is formed on the entire surface, and then a second interconnect trench
7
a
and a first interlayer connection hole
7
b
are formed by photolithography and dry etching.
Then, as shown in
FIG. 1E
, second Ti film
8
and second Cu film
9
are sequentially formed by sputtering, thereby the second interconnect trench
7
a
and the first interlayer connection hole
7
b
are filled with.
Then, as shown in
FIG. 1F
, the second Cu film
9
is removed polishing by the CMP method, and further the second Ti film
8
is removed using diluted hydrofluoric acid. Thus, a second trench interconnect
9
a
on the second layer, and a plug
9
b
connecting between the first trench interconnect
5
a
and the second trench interconnect
9
a
are formed.
This method is also applicable to the case that organic insulation film is used as interlayer insulation film. Such examples are described in D. C. Edelstein et al., Proceedings of 1993 VLSI Multilevel Interconnection Conference, pp.511-513, 1994 and Japanese patent application laid-open No.4-28232 (1992).
A semiconductor device disclosed in Japanese patent application laid-open No.4-28232 is, as shown in
FIG. 2E
, composed of organic insulation film
21
formed on a lower trench interconnect
19
, an interconnect trench and interlayer connection hole
22
formed in the organic insulation film
21
, inorganic insulation film
23
formed on the sidewall of the interconnect trench and interlayer connection hole
22
, and an upper trench interconnect and plug
24
buried into the interconnect trench and interlayer connection hole
22
. Also disclosed is effects to avoid the direct contact between the organic insulation film
21
and the upper trench interconnect and plug
24
, to keep the closeness between the upper trench interconnect and plug
24
and the organic insulation film
21
, and to prevent the defect occurrence caused by moisture absorption of the organic insulation film
21
.
Referring to
FIGS. 2A
to
2
E, a method of forming the trench interconnect disclosed in Japanese patent application laid-open No.4-28232 is explained. Meanwhile, in this method, gold (Au) is used as metal for the trench interconnect and plug
19
,
24
, instead of copper.
First, as shown in
FIG. 2A
, a first interlayer connection hole
13
is formed in inorganic insulation film, which is of silicon oxide, formed on a silicon substrate
11
. Then, tungsten (W) film
14
and Au film
15
are deposited on the entire surface, and while leaving only a region for interconnect, unnecessary part of the tungsten (W) film
14
and Au film
15
is removed by photolithography and dry etching.
Subsequently, as shown in
FIG. 2B
, first organic insulation film
16
of polyimide-system organic resin is formed on the entire surface, and then a first interconnect trench and interlayer connection hole
17
is formed, at part to form an interconnect later, using photolithography and dry etching.
The sidewall of the first interconnect trench and interlayer connection hole
17
is vertical or has such a slope that the trench width decreases in the downward direction and that is close to vertical in the upward direction.
Then, first protection film
18
of inorganic insulation film is deposited on the entire surface, and is etched back by anisotropic reactive ion etching, thereby being left only on the sidewall of the first interconnect trench and interlayer connection hole
17
.
Then, as shown in
FIG. 2C
, Au film is buried into the first interconnect trench and interlayer connection hole
17
by the plating method, thereby a first trench interconnect and plug
19
is formed.
Then, as shown in
FIG. 2D
, second protection film
20
of inorganic insulation film is further formed on the entire surface. Then, by photolithography and dry etching, the second protection film
20
is left covering the first interconnect trench and interlayer connection hole
17
, over the first interconnect trench and interlayer connection hole
17
and in a wider region than the width of the first interconnect trench and interlayer connection hole
17
. The other region of the second protection film
20
is removed.
Then, second organic insulation film
21
of polyimide-system resin film is formed, and a second interconnect trench and interlayer connection hole
22
is formed over and inside the first interconnect trench and interlayer connection hole
17
, with a narrower width than the width of the first interconnect trench and interlayer connection hole
17
. Subsequently, on the sidewall of the second interconnect trench and interlayer connection hole
22
, third protection film
23
of inorganic insulation film is formed.
Then, as shown in
FIG. 2E
, Au film is buried into the second interconnect trench and interlayer connection hole
22
and a second trench interconnect and plug
24
is formed.
After that, the process above is repeated when forming a further multi-layer interconnect.
However, in the method described in S. Lakshminarayanan et al., which uses the inorganic insulation film
6
, there exists the barrier metal film
8
a
around the trench interconnect
9
a
and the plug
9
b
. Therefore, when the interconnect width decreases due to the design rule reduction, there is a problem that the ratio (deposition ratio) of main conductive layer (Cu) to the entire interconnect tends to reduce and thereby effective resistivity tends to increase.
Also, there is a problem that the interlayer connection resistance increases due to the existence of the barrier metal film
8
a.
Further, in the inorganic insulation film
6
, it is difficult to control an increase in capacitance between interconnects or layers occurring with the micro-structuring of device and therefore a delay of circuit cannot be solved. Thus, it is not suitable for the micro-structuring of device.
In contrast with this, in the method described in D. C. Edelstein et al., which uses the organic insulation film, it is possible to control an increase in capacitance between interconnects or la
Lee Eddie
NEC Corporation
Richards N. Drew
Scully Scott Murphy & Presser
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