Static information storage and retrieval – Powering
Reexamination Certificate
2001-02-15
2002-12-17
Nelms, David (Department: 2818)
Static information storage and retrieval
Powering
C365S200000
Reexamination Certificate
active
06496438
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to semiconductor devices, and more particularly, to an internal power supply voltage generation circuit.
A semiconductor memory device, such as a clock synchronous DRAM (SDRAM), has a circuit for generating internal power supply voltage, such as step-up voltage supplied to word lines or negative voltage supplied to a substrate. To answer the recent demand for lower power consumptions of semiconductor memory devices, the voltages of an external power supply and an internal power supply must be decreased. Thus, there is a need for an internal voltage generation circuit that stably supplies a predetermined internal voltage from an external power supply, which voltage is relatively low.
FIG. 1
is a schematic block diagram of an SDRAM
50
having four banks. The SDRAM
50
includes step-up voltage generation circuits
2
a
-
2
h
and control circuits
1
a
-
1
d
, which control the step-up voltage generation circuits
2
a
-
2
h
. The control circuits
1
a
-
1
d
are each associated with one of the banks. Two of the step-up voltage generation circuits
2
a
-
2
h
are connected to each control circuit
1
a
-
1
d
. When the banks are activated, the associated control circuits
1
a
-
1
d
are respectively provided with activation signals A
0
-A
3
. In response to the activation signals A
0
-A
3
, the control circuits
1
a
-
1
d
generate the associated step-up voltage generation circuits
2
a
-
2
h
. The activated step-up voltage generation circuits
2
a
-
2
h
perform a pumping operation based on a clock signal to generate a step-up power supply voltage Vpp. The step-up power supply voltage Vpp is supplied to, for example, the word lines of the associated bank through a common output terminal.
A RAS cycle time (tRC) of the SDRAM
50
is defined by a period that starts when a certain word line is activated and ends when that word line is deactivated and returned to a standby state in which activation of the next word line is enabled. When a word line is activated, read, write, or refresh operations are performed.
The amount of charge consumed during a single RAS cycle time period is substantially constant in the conventional SDRAM
50
. Thus, a shorter RAS cycle time tRC causes the power supply voltage Vpp to consume more current. In other words, the current consumption relative to the power supply voltage Vpp is maximal when the SDRAM is operated in the minimum RAS cycle time tRC of a predetermined guaranteed operation range.
Accordingly, the step-up voltage generation circuits
2
a
-
2
h
each have a sufficient current supply capacity for supplying the associated bank with the maximum current consumption. For example, the step-up voltage generation circuits
2
a
,
2
b
are operated in response to the activation of the first bank to provide the first bank with the power supply voltage Vpp. When the first, second, third, and fourth banks are simultaneously activated, the step-up voltage generation circuits
2
a
-
2
h
are simultaneously activated to provide each of the first to fourth banks with the power supply voltage Vpp. Such operation activates the step-up voltage generation circuits, the number of which corresponds to the number of activated banks, and stably supplies current in correspondence with the current consumption of the activated banks. The power supply voltage Vpp generated by each of the step-up voltage generation circuits
2
a
-
2
h
may be supplied through a power supply line formed independently for each bank.
However, in the conventional SDRAM
50
, the current supplied by the step-up voltage generation circuits becomes excessive as the number of simultaneously activated banks increases.
In
FIG. 2
, ACT denotes an activation command of an arbitrary bank, and PRE denotes a deactivation command of that bank. The time between one ACT and the next ACT is the RAS cycle time. For example, in
FIG. 2
, which indicates the operation of an SDRAM operated at a frequency of 100 MHz, the minimum RAS cycle time tRC of the banks is 60 ns. Accordingly, each of the step-up voltage generation circuits has the current supply capacity to supply sufficient current consumption when the associated bank is operated at the RAS cycle time tRC of 60 ns.
In the first line of
FIG. 2
, a single bank B
0
is activated. In the second line, two banks, B
0
, B
1
are continuously activated. In the first and second lines, each bank is operated in the minimum cycle tRC.
In the third line, three banks B
0
, B
1
, B
2
are continuously activated. In this case, the operational frequency of each bank decreases due to device operation rules and extends the RAS cycle time tRC to 70 ns.
In this manner, as the number of simultaneously activated banks increases, the current supplied by the step-up voltage generation circuits
2
a
-
2
h
becomes excessive, and the pumping operation of the step-up voltage generation circuits
2
a
-
2
h
cause the voltage of the power supply voltage Vpp to become unstable.
A stabilization circuit may be incorporated in the SDRAM to detect and stabilize the power supply voltage Vpp. However, this would increase the circuit area of the SDRAM and the production cost of the SDRAM.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide an internal power supply voltage generation circuit for generating an optimal amount of current supply in accordance with the power consumption of banks.
To achieve the above object, the present invention provides a semiconductor device including a plurality of banks, a plurality of internal power supply voltage generation circuits for generating an internal power supply voltage that is provided to the banks, and at least one control circuit connected to the internal power supply voltage generation circuits for controlling the internal power supply voltage generation circuits. The control circuit adjusts a current supply amount of the internal power supply voltage generation circuits in accordance with a current consumption of at least one of activated ones of the banks.
The present invention also provides a method for generating an internal power supply voltage of a semiconductor device having a plurality of banks and a plurality of internal power supply voltage generation circuits. The plurality of banks include a first bank and a second bank located in the vicinity of the first bank. The plurality of internal power supply voltage generation circuits include at least one internal power supply voltage generation circuit associated with the first bank and at least one second internal power supply voltage generation circuit associated with the second bank. The method includes determining the number of internal power supply voltage generation circuits that are to be activated in accordance with a current consumption of at least one of activated ones of the banks, and providing the at least one of activated ones of the banks with an internal power supply voltage by activating the determined number of internal power supply voltage generation circuits. When the first bank is activated, at least one of the first internal power supply voltage generation circuits and at least one of the second internal power supply voltage generation circuits are activated.
The present invention further provides a method for generating an internal power supply voltage of a semiconductor device having a plurality of banks that include a first bank and a second bank located in the vicinity of the first bank. The method includes assigning a plurality of internal power supply voltage generation circuits to each of the banks. The internal power supply voltage generation circuits generate internal power supply voltage provided to the banks. A current supply capacity of each of the internal power supply voltage generation circuits is equal to or less than a current consumption of when one of the banks is activated. The method further includes activating at least one of the internal power supply voltage generation circuits assigned to the first and second banks when the first bank is activated.
The pre
Arent Fox Kintner Plotkin & Kahn
Fujitsu Limited
Nelms David
Nguyen Thinh T.
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