Semiconductor device and method for fabricating the same

Active solid-state devices (e.g. – transistors – solid-state diode – Heterojunction device – Field effect transistor

Reexamination Certificate

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Details

C257S190000, C257S347000, C257SE27122, C257SE29255

Reexamination Certificate

active

07968912

ABSTRACT:
A semiconductor device includes a substrate, a gate formed over the substrate, a gate spacer provided against first and second sidewalls of the gate, and a source/drain region formed in the substrate proximate to the gate spacer. The source/drain region includes first and second epitaxial layers including Ge, wherein the second epitaxial layer which is formed over an interfacial layer between the first epitaxial layer and the substrate has a higher germanium concentration than that of the first epitaxial layer.

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Ota et al., “Scalable eSiGe S/D technology with less layout dependence for 45-nm generation,”VLSI Technology Digest of Technical Papers(2006).
Thompson et al., “A 90-nm logic technology featuring strained-silicon,”IEEE Transactions on Electron Devices51:1790-1797 (2004).

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