Active solid-state devices (e.g. – transistors – solid-state diode – Heterojunction device – Field effect transistor
Reexamination Certificate
1999-01-06
2001-04-17
Mintel, William (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Heterojunction device
Field effect transistor
C257S194000, C257S195000, C257S507000, C257S622000, C438S167000, C438S421000
Reexamination Certificate
active
06218685
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method for fabricating the same, and more specifically, to a semiconductor device and a method for fabricating an element isolating portion between two or more field effect transistors (FETs) which are semiconductor elements formed on a semi-insulating substrate.
2. Description of the Related Art
A compound semiconductor FET made of a compound such as GaAs or the like is widely used for both digital and analog integrated circuits. Since a compound semiconductor such as GaAs or the like has a higher electron mobility than that of a Si semiconductor, the compound semiconductor FET has an advantage of having a high operation speed suitable for a device which operates in the range from a microwave to a millimeter wave and a high output device. Furthermore, in the case where a compound semiconductor such as GaAs or the like is used as a material of a semi-insulating substrate, the compound semiconductor FET has an advantage of realizing a lower parasitic capacitance than that obtained when using Si as a material of the substrate, and thus reducing an influence on the device.
One example of integrated circuits using a compound semiconductor is a chip used as an amplifier incorporated in a portable phone. Usually, two or more FETs are used in one chip in order to obtain an amplified voltage at a high efficiency and at a high output level. In this chip, a scribe line portion is provided as a result of subscribing a semi-insulating substrate so as to surround the FETs. Moreover, an element isolating portion is provided between the FETs which are placed apart from one another. The element isolating portion is required in order to prevent an interference and an oscillation occurring between FETS. Japanese Laid-Open Publication No. 5-275474, for example, proposes forming a groove reaching a semi-insulating substrate from a surface of a chip between two adjacent FETs.
Hereinafter, an element isolating portion and a scribe line portion of a conventional semiconductor device
600
, and a method for forming the portions will be described with reference to FIG.
6
.
FIG. 6
shows cross-sectional views illustrating steps of a method for forming an element isolating portion
69
and a scribe line portion
70
of the conventional semiconductor device
600
. In
FIG. 6
, parts A
1
to A
5
show steps of forming the element isolating portion
69
, and parts B
1
to B
5
show steps of forming the scribe line portion
70
. Parts A
1
, A
2
, A
3
, A
4
and A
5
and parts B
1
, B
2
, B
3
, B
4
and B
5
show corresponding steps, respectively.
As shown in parts A
5
and B
5
in
FIG. 6
, the conventional semiconductor device
600
includes a semi-insulating substrate
65
; a buffer layer
64
provided on the semi-insulating substrate
65
; an interlevel film
63
provided on the buffer layer
64
; an electrode
62
provided on the interlevel film
63
; and a protective film
61
provided on the buffer layer
64
covering ends of the electrode
62
and the interlevel film
63
, and formed so that a top surface of the electrode
62
is partially exposed so as to form electrode windows
66
. The semi-insulating substrate
65
is made of GaAs, and the buffer layer
64
includes an undoped GaAs film (thickness: 5000 Å), an undoped Al
0.2
Ga
0.8
As film (thickness: 2000 Å), and an undoped GaAs film (thickness: 1000 Å) sequentially provided in this order from the bottom. The interlevel film
63
includes an upper layer made of SiN having a thickness of 5000 Å and a lower layer made of SiO
2
having a thickness of 5000 Å. The electrode
62
is made of Au, and the protective film
61
is made of SiN having a thickness of 5000 Å. As shown in part A
5
in
FIG. 6
, the semiconductor device
600
has the element isolating portion
69
penetrating the buffer layer
64
and reaching an inside of the semi-insulating substrate
65
. In the vicinity of the element isolating portion
69
, the buffer layer
64
and the semi-insulating substrate
65
are exposed to outside air. Furthermore, as shown in part B
5
in
FIG. 6
, the protective film
61
is partially disconnected on the buffer layer
64
so as to form the scribe line portion
70
. In the vicinity of the scribe line portion
70
, the buffer layer
64
is exposed to outside air.
The buffer layer
64
has a function of reducing a current leakage to the substrate
65
through a channel. The interlevel film
63
inactivates the surface of the buffer layer
64
so as to obtain the stability thereof, and prevents the buffer layer
64
from adsorbing molecules in the air.
Hereinafter, a conventional method for fabricating the semiconductor device
600
having the element isolating portion
69
and the scribe line portion
70
will be described in detail.
It should be noted that the conventional method for fabricating FETs will not be shown in drawings because it is known to those skilled in the art.
After forming the metal layers for a gate, a source and a drain on the active layer, the interlevel film
63
is formed so as to cover an active layer on the buffer layer
64
. Subsequently, a contact hole is formed in the interlevel film
63
so as to reach the metal layer. Then, the electrode
62
is formed on the interlevel film
63
so as to fill the contact hole, thereby forming a FET. Any appropriate method can be employed in fabricating the FETs.
Then, a first resist layer
68
-
1
(parts A
1
and B
1
of
FIG. 6
) used for etching the interlevel film
63
is formed in a dark room by a resist coater. The first resist layer
68
-
1
has an opening having a width of 90 &mgr;m at a position where the element isolating portion
69
will be formed and an opening having a width of 80 &mgr;m at a position where the scribe line portion
70
will be formed.
Next, the interlevel film
63
including the SiN (upper) layer and the SiO
2
(lower) layer is etched, as shown in parts A
1
and B
1
in
FIG. 6
, at positions where the element isolating portion
69
and the scribe line portion
70
will be formed. In this step, the SiN layer is etched by dry etching with CF
4
, and subsequently, the SiO
2
layer is etched by wet etching with hydrofluoric acid. Then, the first resist layer
68
-
1
is removed by a resist remover. Thereafter, as shown in parts A
2
and B
2
in
FIG. 6
, a SiN layer is grown by plasma CVD on the buffer layer
64
covering the interlevel film
63
and the electrode
62
so as to form the protective film
61
having a thickness of 5000Å.
Subsequently, as shown in parts A
3
and B
3
in
FIG. 6
, a second resist layer
68
-
2
used for forming the electrode windows
66
functioning as a gate, a source and a drain of the FET on the Au electrode
62
is formed on the protective film
61
by a resist coater in a dark room. The second resist layer
68
-
2
has openings at positions where the electrode windows
66
, the element isolating portion
69
and the scribe line portion
70
will be later formed. Next, still referring to parts A
3
and B
3
in
FIG. 6
, the protective film
61
is etched by dry etching with CF
4
using the second resist layer
68
-
2
as a mask in order to form openings at positions where the element isolating portion
69
and the scribe line portion
70
will be formed. The second resist layer
68
-
2
has an opening having a width of 85 &mgr;m at a position where the element isolating portion
69
will be formed and an opening having a width of 75 &mgr;m at a position where the scribe line portion
70
will be formed. The width of each opening of the second resist layer
68
-
2
is slightly smaller than that of the first resist
68
-
1
because the protective film
61
needs to cover the interlevel film
63
.
After removing the second resist layer
68
-
2
by a resist remover, a third resist layer
68
-
3
(part A
4
and B
4
in
FIG. 6
) used for forming the element isolating portion
69
is formed by a resist coater in a dark room. The third resist layer
68
-
3
has an opening h
Matsushita Electronics Corporation
Mintel William
Ratner & Prestia
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