Active solid-state devices (e.g. – transistors – solid-state diode – Physical configuration of semiconductor – Mesa structure
Patent
1998-04-16
2000-03-07
Wojciechowicz, Edward
Active solid-state devices (e.g., transistors, solid-state diode
Physical configuration of semiconductor
Mesa structure
257296, 257314, 257401, 438225, 438697, 438700, H01L 2972
Patent
active
060344164
ABSTRACT:
The top surface of a substrate in a peripheral circuit region is at a level that is higher than the top surface of the substrate in a memory cell region and that is substantially equal to the top surface of a floating gate electrode. A control gate electrode is formed on the floating gate electrode via a gate insulator film, and a gate electrode is formed on the substrate in the peripheral circuit region via a gate insulator film. The top surface of a buried insulator film for trench isolation may be at a level equal to the top surface of the floating gate electrode or to the top surface of an underlying film if the control gate electrode is formed of a multi-layer film. A level difference between the control gate electrode in the memory cell region and the gate electrode in the peripheral circuit region can be reduced, and thus fine patterns can be formed in these regions. In a flash-integrated logic LSI incorporating a nonvolatile memory cell, a density can be increased in the memory cell region and the peripheral circuit region and the costs can be reduced.
REFERENCES:
patent: 5714793 (1998-02-01), Cartagena et al.
Arai Masatoshi
Moriwaki Masaru
Segawa Mizuki
Uehara Takashi
Ukeda Takaaki
Matsushita Electirc Industrial Co., Ltd.
Wojciechowicz Edward
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