Active solid-state devices (e.g. – transistors – solid-state diode – Heterojunction device – Light responsive structure
Reexamination Certificate
2007-12-11
2007-12-11
Tsai, H. Jey (Department: 2812)
Active solid-state devices (e.g., transistors, solid-state diode
Heterojunction device
Light responsive structure
C257S200000, C257SE33033
Reexamination Certificate
active
10456901
ABSTRACT:
An insulating-gate semiconductor device has a first nitride semiconductor layer formed over a substrate and an insulating oxidation layer obtained by oxidizing a second nitride semiconductor layer formed on the first nitride semiconductor layer. A gate electrode is formed on the insulating oxidation layer.
REFERENCES:
patent: 4912062 (1990-03-01), Verma
patent: 5929467 (1999-07-01), Kawai et al.
patent: 6037205 (2000-03-01), Huh et al.
patent: 6140169 (2000-10-01), Kawai et al.
patent: 6190508 (2001-02-01), Peng et al.
patent: 6324200 (2001-11-01), Kamiyama et al.
patent: 6346450 (2002-02-01), Deleonibus et al.
patent: 6349454 (2002-02-01), Manfra et al.
patent: 6391727 (2002-05-01), Park
patent: 6423986 (2002-07-01), Zhao
patent: 6492669 (2002-12-01), Nakayama et al.
patent: 6528370 (2003-03-01), Suzuki et al.
patent: 6531718 (2003-03-01), Inoue et al.
patent: 2001/0023964 (2001-09-01), Wu et al.
patent: 2003/0053505 (2003-03-01), Bour et al.
patent: 01-137-072 (2001-09-01), None
patent: 55-138238 (1980-10-01), None
patent: 11-501463 (1999-02-01), None
patent: 11-163334 (1999-06-01), None
patent: 11-204778 (1999-07-01), None
patent: 2000-068498 (2000-03-01), None
patent: 2000-164926 (2000-06-01), None
patent: 2000-252458 (2000-09-01), None
patent: 97/24752 (1997-10-01), None
Masato, et al., “Novel High Drain Breakdown Voltage Algan HFETS Using Selective Thermal Oxidation Process”, Dec. 2-5, 2000, International Electron Devices Meeting—San Francisco, CA, IDEM. Technical Digest, pp. 377-380 (2000).
Readinger et al.,An Investigation of the Thermal Oxides on Gallium Nitride Grown Under Various Oxidizing Ambients, Nov. 1, 1998, Electrochemical Society Proceedings—New York, NY, vol. 98, No. 18, pp. 215-224 (1998).
Inoue et al., “Novel Gan-Based MOS HFETS With Thermally Oxidized Gate Insulator”, Dec. 2-5, 2001, International Electron Devices Meeting—New York, NY, IDEM Technical Digest, pp. 577-580 (2001).
European Search Report for Application No. EP-02-00-3376 dated Feb. 4, 2004.
First Office Action from the People's Republic of China Application No. 02105253.0 dated Nov. 19, 2004.
Inoue et al.; “Novel GaN-based MOS HEFTs with thermally oxidize gate insulator”, Electron Devices Meeting, 2001. IEDM Technical Digest. International; Dec. 2, 2001-Dec. 15, 2001; Washington D.C., USA; pp. 25.2.1-25.2.4.
Office Action dated Dec. 26, 2006 issued in corresponding Japanese patent application.
Ikeda Yoshito
Inoue Kaoru
Masato Hiroyuki
Matsuno Toshinobu
Nishii Katsunori
Matsushita Electric - Industrial Co., Ltd.
Studebaker Donald R.
Tsai H. Jey
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