Semiconductor device and method for fabricating the same

Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Including adhesive bonding step

Reexamination Certificate

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Details

C438S597000, C438S622000, C438S624000

Reexamination Certificate

active

11023348

ABSTRACT:
The present invention relates to a semiconductor device with an improved contact margin between an interconnection line and a bit line and a method for fabricating the same. The semiconductor device includes: a bit line structure formed on a substrate and having a number of bit lines and a pad; a first inter-layer insulation layer formed on the bit line structure and the substrate and having a first opening exposing the pad; a conductive layer formed on the first inter-layer insulation layer and patterned to be a middle pad filled into the first opening and a plate electrode of a capacitor; a second inter-layer insulation layer formed on the first inter-layer insulation layer and the patterned conductive layer and having a second opening exposing the middle pad; and a metal layer filled into the second opening to form an interconnection line contacted to the pad.

REFERENCES:
patent: 5929469 (1999-07-01), Mimoto et al.
patent: 6329281 (2001-12-01), Lytle et al.
patent: 6844600 (2005-01-01), McQueen
patent: 6962771 (2005-11-01), Liu et al.
patent: 2005/0085070 (2005-04-01), Park
patent: 1997-0054004 (1997-10-01), None
patent: 1998-066718 (1998-10-01), None
Korean Office Action, Dec. 16, 2005.

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