Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
2003-07-31
2004-07-20
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S435000, C438S400000, C438S404000, C438S236000, C438S295000, C438S296000, C438S219000, C257S622000, C257S374000
Reexamination Certificate
active
06764921
ABSTRACT:
BACKGROUND OF THE INVENTION
(a) Field of the Invention
The present invention relates to a semiconductor device and a method for fabricating the same, and more particularly to a semiconductor device including a trench isolation structure and a method for fabricating the same.
(b) Description of the Related Art
One of methods for electrically isolating elements on a semiconductor substrate is a trench isolation method. The trench isolation method is one in which a trench having an appropriate depth is dug in a region of the semiconductor substrate between elements and an insulator is buried therein so as to isolate the elements. This method is disclosed in Japanese Unexamined Patent Publication No. 11-26571, for example.
A method for fabricating a trench isolation structure according to a known semiconductor device will be described hereinafter with reference to
FIGS. 5A through 5F
.
FIGS. 5A through 5F
are cross sectional views showing process steps for fabricating the trench isolation structure according to the known semiconductor device.
First, in the process step shown in
FIG. 5A
, the surface of the semiconductor substrate
51
is oxidized so as to form a thermal oxide film
52
. Subsequently, semiconductor nitride is deposited on the thermal oxide film
52
using a chemical vapor deposition (CVD) method, thereby forming a nitride film
53
.
Next, in the process step shown in
FIG. 5B
, a mask
54
having an opening on an isolation region is formed on the nitride film
53
by photolithography. Anisotropic etching is performed using the mask
54
, whereby the semiconductor substrate
51
is etched through the nitride film
53
and the thermal oxide film
52
to a predetermined depth so as to form a trench
55
.
Next, in the process step shown in
FIG. 5C
, after the mask
54
is removed, a first oxide film
56
is formed on the surface of the semiconductor substrate
51
exposed in the trench
55
by a thermal oxidation method.
Next, in the process step shown in
FIG. 5D
, a second oxide film
57
is formed on the substrate to fill the trench
55
by a high-density plasma CVD method or the like.
Subsequently, in the process step shown in
FIG. 5E
, the second oxide film
57
is planarized by a chemical mechanical polishing (CMP) method or the like. The second oxide film
57
is planarized until the top of the nitride film
53
is exposed.
Next, in the process step shown in
FIG. 5F
, the nitride film
53
and the thermal oxide film
52
are removed by selective etching, thereby forming a trench isolation
58
having the trench
55
filled with the first oxide film
56
and the second oxide film
57
. When the thermal oxide film
52
is removed, the upper part of the second oxide film
57
is similarly removed. More particularly, since the upper edge of the second oxide film
57
is easily removed, a depression
59
is formed.
However, the known semiconductor device having the above-mentioned trench isolation structure causes the following problems.
After the formation of the trench isolation
58
, the known semiconductor device is formed through a thermal oxidation process step for forming a gate dielectric and a heat treating process step such as thermal diffusion after impurity ion implantation. In such process steps, oxidation progresses in a portion of the semiconductor substrate contacting the upper end of the trench isolation structure.
FIG. 6
is a cross sectional view showing a process step for thermally oxidizing the upper part of the semiconductor substrate to form a gate dielectric
60
according to the known semiconductor device. As shown in
FIG. 6
, oxygen is supplied not only from above but also from the trench isolation
58
to the upper end of an element formation region of the semiconductor substrate
51
, resulting in overoxidized regions
61
grown therein. When the overoxidized regions
61
are grown, the volumes of the regions expand so that stresses are produced, and thus crystal defects easily take place in the semiconductor substrate. Therefore, a leakage current easily flows through the crystal defects so that the isolation capability might be reduced.
When an element formed in the element formation region of the semiconductor substrate
51
is an N-type MISFET (metal insulator semiconductor field effect transistor), the mobility of electrons is decreased due to the stresses given from the overoxidized regions
61
, whereby the drive current of the transistor is also reduced.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a semiconductor device in which stresses given from a trench isolation to element formation regions can be suppressed to decrease a leakage current resulting from crystal defects and a method for fabricating the same.
It is another object of the present invention to provide a high reliability and high performance semiconductor device preventing the drive current of an n-type MISFET from being reduced.
A semiconductor device of the present invention comprises: a semiconductor layer including an element formation region; a trench isolation surrounding the element formation region of the semiconductor layer; and a coating film having the property of suppressing passage of oxygen, said coating film covering at least a portion of the trench isolation and a portion of the element formation region astride the border between the trench isolation and the element formation region.
Thereby, it becomes hard that the upper edge of the element formation region of the semiconductor layer is oxidized, and thus it becomes hard that an expansion of the volume of the upper edge takes place. Therefore, the occurrence of a stress can be suppressed, thereby suppressing the occurrence of a leakage current.
The coating film directly contacts the semiconductor layer. Therefore, oxidation of the upper edge of the semiconductor layer is suppressed in a process step for fabricating a semiconductor device.
The semiconductor device further comprises an element including: source/drain regions provided in the element formation region of the semiconductor layer; a gate dielectric formed by thermally oxidizing the top of the element formation region of the semiconductor layer; and a gate electrode provided on the gate dielectric. In this case, even when the semiconductor layer is thermally oxidized to form the gate dielectric, oxidation of the upper edge of the element formation region could be reduced.
The element may be an n-type MISFET. In this case, the occurrence of a stress is suppressed to improve the mobility of electrons. Therefore, the drive current thereof can be improved.
It is preferable that the coating film is formed of silicon nitride.
A plurality of the element formation regions may be provided, and the coating film may cover the top of the trench isolation and extend to the two element formation regions of the semiconductor layer adjacent to the trench isolation.
A depression is provided on the upper edge of the trench isolation, and the coating film extends from the bottom of the depression to the top of the element formation region. Therefore, the surface of the substrate is more planarized.
A first method for fabricating a semiconductor device of the present invention comprises the steps of: (a) forming a trench isolation surrounding an element formation region in a semiconductor layer; (b) forming a coating film having the property of suppressing passage of oxygen to lie from the top of the semiconductor layer to the top of the trench isolation; and (c) removing a portion of the coating film to form a partial coating film that covers at least a portion of the trench isolation and a portion of the element formation region of the semiconductor layer astride the border between the trench isolation and the element formation region.
Thereby, it becomes hard that the upper edge of the element formation region of the semiconductor layer is oxidized after the step (c), and thus it becomes hard that an expansion of the volume of the upper edge takes place. Since the occurrence of a stress can therefore be suppressed,
Imade Masahiro
Umimoto Hiroyuki
Keshavan Belur
Matsushita Electric - Industrial Co., Ltd.
McDermott & Will & Emery
Smith Matthew
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