Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Reexamination Certificate
2003-07-15
2004-07-27
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
C257S173000, C257S328000, C257S355000, C257S546000, C438S118000, C438S268000, C438S309000, C438S622000
Reexamination Certificate
active
06768201
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention related to semiconductor devices and methods for fabricating a semiconductor device, and more particularly relates to a semiconductor device used for protecting an internal circuit from electrostatic destruction and a method for fabricating the same.
In a semiconductor device, signals are transmitted and received between an internal circuit and the outside of the device via an input/output pad. From the input/output pad to the internal circuit, not only signals for driving the internal circuit but also static electricity unexpectedly generated outside of the device is supplied. When large static electricity is supplied to the internal circuit, elements provided in the internal circuit may be damaged.
To avoid such electrostatic destruction of the internal circuit, an electrostatic protection device or an electrostatic protection circuit including an electrostatic protection device are provided between an internal circuit and an input/output pad in a semiconductor device. As a widely used electrostatic protection device, a parasitic bipolar transistor having the source (S)—substrate (B)—drain (D) structure for an MISFET is known.
Hereinafter, the structure of an electrostatic protection device will be described with reference to FIG.
9
.
FIG. 9
is a cross-sectional view schematically illustrating the structure of a known semiconductor device using an npn type parasitic bipolar transistor.
As shown in
FIG. 9
, in the known semiconductor device, provided are an internal circuit
81
and an input/output pad
82
which allows signal transmission and reception between the internal circuit
81
and the outside of the semiconductor device, an electrostatic protection device
83
connected between the internal circuit
81
and the input/output pad
82
and having an n-type MISFET structure. The electrostatic protection device
83
includes a semiconductor substrate
90
, source and drain regions
91
and
92
provided in the semiconductor substrate
90
so as to be spaced apart from each other, a source electrode
93
provided on the source region
91
, a drain electrode
94
provided on the drain region
92
, a gate insulating film
95
provided on the semiconductor substrate
90
, a gate electrode
96
provided on the gate insulating film
95
, a sidewall spacer
97
provided on each of the side faces of the gate insulating film
95
, and a resistance
98
connected to the gate electrode
96
.
The drain electrode
94
of the electrostatic protection device
83
is connected between the internal circuit
81
and the input/output pad
82
. Meanwhile, the gate electrode
96
, the source electrode
93
and the semiconductor substrate
90
are connected to a ground potential
99
to be grounded. When the electrostatic protection device
83
functions as a parasitic bipolar transistor, the drain region
92
serves as a collector
101
, the source region
91
serves as an emitter
100
, and a region of the semiconductor substrate
90
located between the source and drain regions
91
and
92
serves as a base
102
. Note that a substrate resistance
104
is illustrated in
FIG. 9
to schematically show that the semiconductor substrate
90
functions as a resistance when the electrostatic protection device
83
functions as a parasitic bipolar transistor.
Next, the operation mechanism of the electrostatic protection device
83
will be described with reference to FIG.
9
. When an excessive negative voltage caused by static electricity is applied from the outside of the semiconductor device to the input/output pad
82
, an electric current flows from the ground potential
99
in the direction toward the input/output pad
82
so that static electricity is discharged. The electric current flows according to forward characteristics of a pn junction formed by the n-type drain region
92
of the semiconductor substrate
90
and a p-type region of the semiconductor substrate
90
connected to the ground potential
99
. Thus, the excessive negative voltage applied to the input/output pad
82
is clamped. Therefore, the internal circuit is protected from the excessive voltage.
On the other hand, when an excessive positive voltage is applied to the input/output pad
82
, the operation mode of the electrostatic protection device
83
is turned from an MISFET mode to a bipolar transistor mode. This operation will be specifically described hereinafter. When an excessive voltage is applied from the input/output pad
82
to the drain electrode
94
, an electric current flows to the ground potential
99
via the drain electrode
94
, the semiconductor substrate
90
and the source electrode
93
so that static electricity is discharged. As the voltage applied to the drain electrode
94
is increased, impact ionization is accelerated at the edge of drain region
92
of the n-type MISFET and therefore a substrate current
103
is gradually increased. When the substrate current
103
flows in the substrate resistance
104
, a voltage drop occurs to increase the potential of the base
102
. When the base potential is increased to a certain extent, the parasitic bipolar transistor is conducted so that a large current flows from the collector
101
(i.e., the drain region
92
) to the emitter
100
(i.e., the source region
91
). A voltage applied to the drain to turn the operation mode of the electrostatic protection device from the operation mode as an MISFET to the operation mode as a bipolar transistor is called “trigger voltage.”
FIG. 10
is a graph showing the relation between the voltage level and the current level in a transistor exhibiting a snap-back characteristic. In the electrostatic protection device
83
, a current flows according to the snap-back characteristic shown in FIG.
10
. Thus, a voltage applied to the drain electrode
94
is suppressed lower than the trigger voltage. Normally, the trigger voltage is lower than the breakdown voltage of the internal circuit device and therefore the internal circuit is protected from an excessive voltage.
Note that the resistance
98
of
FIG. 9
has the effect of reducing the trigger voltage. The principle of the effect will be described hereinafter. In general, the drain region
92
of the MISFET is formed so as to overlap with an edge portion of the gate electrode
96
. Thus, a capacitance exists between the gate and the drain. When an excessive positive voltage caused by static electricity is applied to the drain electrode
94
with the capacitance formed, a charge current generated due to the capacitance momentarily flows from the drain electrode
94
to the ground potential
99
via the gate electrode
96
and the resistance
98
. Accordingly, a voltage drop by the resistance
98
occurs and thus the potential of the gate electrode
96
is increased. When the potential of the gate electrode
96
is increased, the current flowing between the drain and the source is increased, thus accelerating impact ionization. Therefore, the substrate current
103
is increased, and thus a large voltage drop by the substrate resistance
104
occurs to increase the base potential. As a result, the parasitic bipolar transistor is easily conducted. As has been described, with the resistance
98
provided, the level of a trigger voltage when an excessive positive voltage caused by static electricity is applied can be reduced.
Note that the above-described electrostatic protection device was disclosed in Japanese Unexamined Patent Publication No. 3-73567.
In the known semiconductor device, however, the following problems arise.
Generally, MISFETs are designed so that deterioration of the gate insulating film therein due to injection of hot carriers is suppressed. More specifically, in MISFETs, impurity profiles are formed so that an electric field at the edge of the drain can be relaxed. Accordingly, the substrate current generated through impact ionization is reduced and thus the voltage drop by a substrate resistance is reduced. This results in an increase in the trigger voltage. Therefore, it becomes difficult to
Imade Masahiro
Miyata Satoe
Umimoto Hiroyuki
Huynh Andy
Matsushita Electric - Industrial Co., Ltd.
Nelms David
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