Semiconductor device manufacturing: process – Making passive device – Stacked capacitor
Reexamination Certificate
1997-11-05
2003-06-10
Zarabian, Amir (Department: 2822)
Semiconductor device manufacturing: process
Making passive device
Stacked capacitor
C438S253000, C438S241000, C257S300000, C257S306000
Reexamination Certificate
active
06576527
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a fabrication technology of a semiconductor device, more specifically to a semiconductor device having a DRAM-type memory device and a method for fabricating the same.
A DRAM is a semiconductor memory device which can be formed by one transistor and one capacitor. Various structures for DRAMs of higher density and higher integration, and methods for fabricating DRAMs of such structures have been conventionally studied.
Recently in the field of the fabrication of the DRAM-type semiconductor device the competition among makers has become severe, and it is an important subject how to fabricate DRAM-type semiconductor devices of higher integration and higher achievement at low costs.
To this end, the capacitor requires a simpler structure. Structures which are simple and can secure sufficient capacities are studied. One of such structures of the capacitor uses a pillar-shaped conductor as the storage electrode.
A semiconductor device using the pillar-shaped conductor as the storage electrode will be explained with reference to FIG.
52
.
On a semiconductor substrate
10
there are formed source/drain diffused layers independent of each other. A gate electrode
18
is formed on the semiconductor substrate
10
between the source/drain diffused layers
20
,
22
through a gate oxide film. Thus a memory cell transistor comprising a gate electrode
18
, the source/drain diffused layers
20
,
22
is formed.
An inter-layer insulation film
24
with a through-hole formed in above the source/drain diffused layer
20
is formed on the semiconductor substrate
10
with the memory cell transistor formed on.
In the through-hole a storage electrode
46
is formed with the bottom connected to the source/drain diffused layer
20
and protruded onto the inter-layer insulation film
24
. An opposed electrode
56
is formed on the upper surface and the sidewalls of the storage electrode
46
through a dielectric film
52
, and the storage electrode
46
, the dielectric film
52
and the opposed electrode
56
constitute a capacitor.
On the semiconductor substrate
10
with the memory cell transistor and the capacitor interconnections
60
,
62
are formed trough an inter-layer insulation film
68
. The interconnection
60
is connected to the opposed electrode
56
, and the interconnection
62
is connected to the semiconductor substrate
10
in a peripheral circuit region.
Thus a DRAM comprising one transistor and 1 capacitor is formed.
As described above, the conventional semiconductor device shown in
FIG. 52
has the storage electrode
46
constituting the capacitor in the simple pillar-shaped structure, which can be easily formed by one film forming step and one patterning step. Thus the capacitor forming step can be drastically simplified, and the forming costs can be accordingly lower.
However, in the conventional semiconductor device using the pillar-shaped storage electrode
46
the memory cell region is higher than the peripheral circuit region by a height of the storage electrode
46
, which makes it difficult to open a contact hole for connecting the interconnection
62
to a peripheral circuit.
That is, usually a contact hole for connecting the interconnection to the peripheral circuit is formed through the inter-layer insulation film
48
formed on the storage electrode
46
(FIG.
52
). However because of a large height difference of the inter-layer insulation film
68
between the memory cell region and the peripheral region, in simultaneously forming the contact hole to be opened on the opposed electrode
56
and the contact hole to be opened in the peripheral region, a sufficient depth of focus cannot be obtained in the contact hole opening step and the metallization step, which required micronized processing precision. Neither of the two contact holes cannot be correctly formed.
To ensure a sufficient depth of focus, the inter-layer insulation film
68
is planarized by, e.g., CMP (chemical mechanical polishing) method. However, the contact hole in the peripheral circuit region has a very high aspect ration, which makes it difficult to open the contact hole. It also makes it difficult to bury the interconnection in the contact-hole (FIG.
53
).
To the semiconductor device fabrication process it is important for lower fabrication costs how to decrease lithography steps, and semiconductor structures and methods for fabricating the same which can decrease lithography steps are needed.
Each lithography step needs a pattern layout which considers a alignment allowance. For micronization of the devices, new means which enables the pattern layout to be conducted without considering the alignment allowance is needed.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor device and a method for fabricating the same which can form a memory cell in a simple structure and by a simple fabrication process, and which are superior in alignment with a process for forming a contact hole in a peripheral circuit region.
The above-descried object is achieved by a semiconductor device including a memory cell region and a peripheral circuit region of a semiconductor substrate, comprising: a transfer transistor formed in the memory cell region; a capacitor connected to one of diffused layers of the transfer transistor and including a storage electrode formed of a first conducting layer, a dielectric film covering a sidewall of the storage electrode and an opposed electrode formed on the dielectric film; a first conducting plug formed of the first conducting layer and connected to the peripheral circuit region of the semiconductor substrate; and a first interconnection electrically connected to the first conducting plug. This structure of the semiconductor device allows the region interconnecting the first interconnection and the semiconductor substrate to be raised by the first conducting plug, which makes it unnecessary to open the contact hole deep enough to reach the semiconductor substrate so as to bury the first interconnection, with the result that the etching step and the interconnection forming step can be simple. Also in forming the interconnection connected to the opposed electrode simultaneously with the first interconnection, because the opposed electrode and the first conducting plug are substantially on the same level, the contact hole and the interconnection can be patterned irrespective of depth of focus. Because the first conducting plug can be formed of the same conducting layer as the storage electrode, the first conducting plug can be formed without making fabrication process complicated.
In the above-described semiconductor device, it is preferable that the storage electrode includes a second conducting layer on a surface thereof contacting the dielectric film. This structure of the semiconductor device makes it possible to maintain an operational speed of the semiconductor device without degrading characteristics of the capacitor. That is, it is preferred that the first conducting plug interconnecting the first interconnection and the semiconductor substrate has smaller resistance value because a resistance value of the first conducting plug influences the operational speed of the semiconductor device. On the other hand, it is required that a storage electrode have good compatibility with a dielectric film, and to this end, because the dielectric film and the first conducting plug are formed of the same material, a material thereof must be selected based on both conditions. However, this structure makes it possible to select a material low resistance as a material of the first conducting plug without considering a material of the storage electrode. Thus, without degrading characteristics of the capacitor, the semiconductor device can retain an operational speed.
In the above-described semiconductor device, it is preferable that a plurality of the storage electrodes are provided, and the opposed electrode is buried between said a plurality of the storage electrodes. This structure of t
Armstrong Westerman & Hattori, LLP
Vockrodt Jeff
Zarabian Amir
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