Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated...
Reexamination Certificate
2001-02-07
2003-01-28
Chaudhuri, Olik (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
C257S506000, C257S510000
Reexamination Certificate
active
06512282
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device, which includes a buried gate electrode and an isolation film and source/drain contacts that are self-aligned with the buried gate electrode, and also relates to a method for fabricating a device with such a structure.
Recently, the number of semiconductor devices that can be integrated on a single chip has increased by leaps and bounds as those devices have been tremendously downsized. As this miniaturization trend accelerates, a contact hole (or a contact formed by filling in the hole with a conductor), provided for interconnecting the gate electrode or doped layer of an MIS semiconductor device to an interconnection layer, has further reduced its size every time size generations alternate.
To reduce a margin needed in overlaying masks one upon the other during a photolithographic process and thereby further increase the number of semiconductor devices integrated, various methods for forming contacts self-aligned with a gate electrode have been researched and developed vigorously. Those contacts will be herein called “self-aligned contacts”. Hereinafter, a semiconductor device including the known self-aligned contacts and its fabrication process will be described.
FIG. 40
illustrates a cross section of a known MIS semiconductor device, including self-aligned contacts, taken in the channel direction (i.e., the gate length direction) thereof. As shown in
FIG. 40
, a trench isolation film
104
is provided on an Si substrate
101
and an MIS transistor is formed in an active region surrounded by the isolation film
104
. The MIS transistor includes: a gate insulating film
105
of SiO
2
; a gate electrode
106
of polysilicon; an upper insulating film
107
of SiN; a nitride sidewall
109
of SiN; LDD regions
108
; and heavily doped source/drain regions
110
. The gate insulating film
105
, gate electrode
106
and upper insulating film
107
are stacked in this order on the substrate
101
and the side faces of the gate electrode
106
and upper insulating film
107
are covered with the sidewall
109
. The LDD regions
108
and heavily doped source/drain regions
110
are defined within the substrate
101
by introducing dopants thereto. Contacts
112
of tungsten, for example, are formed to pass through an interlevel dielectric film
111
over the substrate
101
and to reach the heavily doped source/drain regions
110
. Depending on the direction of mask misalignment, these contacts
112
come into partial contact with the upper insulating film
107
and sidewall
109
. And these contacts
112
are self-aligned contacts that have been aligned with the gate electrode
106
automatically.
FIGS. 41A through 41E
are cross-sectional views illustrating respective process steps for fabricating the MIS semiconductor device including the known self-aligned contacts.
First, in the process step shown in
FIG. 41A
, a stopper insulating film
102
, which may be a multilayer structure consisting of silicon dioxide and silicon nitride films, is deposited on an Si substrate
101
. Then, parts of the stopper insulating film
102
and substrate
101
, where the trench isolation will be formed, are etched to a predetermined depth, thereby forming a trench
103
in the substrate
101
.
Next, in the process step shown in
FIG. 41B
, a CVD silicon dioxide film is deposited over the substrate and has its surface planarized by a chemical/mechanical polishing (CMP) process using the stopper insulating film
102
as a polish stopper. In this manner, the trench
103
is filled in with the CVD silicon dioxide film, thereby forming the trench isolation film
104
. As a result, the upper surfaces of the isolation film
104
and stopper insulating film
102
are planarized to the same level. Once a desired planarity is attained, the stopper insulating film
102
is removed.
Then, in the process step shown in
FIG. 41C
, the exposed surface of the substrate
101
is thermally oxidized, thereby forming a gate insulating film
105
of SiO
2
. Subsequently, after polysilicon and silicon nitride film have been stacked in this order over the substrate, those two films are patterned by lithography and dry etching techniques to form a gate electrode
106
and an upper insulating film
107
in the active region. Thereafter, dopants ions are lightly implanted into the substrate
101
using the upper insulating film
107
and isolation film
104
as a mask, thereby defining LDD regions
108
self-aligned with the gate electrode
106
.
Next, in the process step shown in
FIG. 41D
, a silicon nitride film is deposited over the substrate and then etched back, thereby forming a nitride sidewall
109
over the side faces of the upper insulating film
107
and gate electrode
106
. Then, dopants ions are heavily implanted into the substrate
101
using the upper insulating film
107
, sidewall
109
and isolation film
104
as a mask, thereby defining heavily doped source/drain regions
110
self-aligned with the gate electrode
106
.
Subsequently, in the process step shown in
FIG. 41E
, a relatively thick CVD silicon dioxide film is deposited over the substrate and then planarized by a CMP process, thereby forming an interlevel dielectric film
111
. Thereafter, contact holes, reaching the heavily doped source/drain regions
110
, are opened through the interlevel dielectric film
111
and then filled in with a conductor, thereby forming source/drain contacts
112
that make electrical contact with the heavily doped source/drain regions
110
.
According to this method, when the contact holes are opened through the interlevel dielectric film
111
so as to reach the heavily doped source/drain regions
110
, the gate electrode
106
has already been covered with the SiN upper insulating film
107
and nitride sidewall
109
. Thus, even if those holes are formed to overlap with the gate electrode
106
due to mask misalignment, the silicon nitride film serves as an etch stopper. As a result, the source/drain contacts
112
can be formed as self-aligned contacts without making the holes partially etch the gate electrode
106
.
The semiconductor device with the known self-aligned contacts and its fabrication process, however, has the following drawbacks.
Firstly, in the known method of making the self-aligned contacts, the source/drain contacts must be formed within the contact holes that have been prepared by lithography and dry etching processes. Thus, the size of the source/drain contacts can be reduced to no smaller than the minimum opening size of a resist pattern for use in an exposure process.
The self-aligning technique for the known self-aligned contacts was developed to form the contact holes, reaching the source/drain regions, without getting the gate electrode etched even if those holes horizontally overlap with the gate electrode due to the placement error of photomasks for use in making the holes. This is because the upper and side faces of the gate electrode have already been covered with the silicon nitride film when those holes are opened. That is to say, this self-aligned contact making method was designed to increase an allowable mask overlay margin for a photolithographic process for forming the contact holes. Thus, the size of the contact holes themselves, in which the contacts should be formed by filling the holes with a conductor, is determined by the minimum opening size of a resist pattern.
FIG. 42A
is a cross-sectional view illustrating an MIS transistor including the known self-aligned contacts along with the sizes of respective parts of the transistor.
FIG. 42B
is a plan view illustrating a photomask used for forming the contact holes.
As shown in
FIG. 42A
, the contact holes
114
reaching the heavily doped source/drain regions
110
are formed by etching the interlevel dielectric film
111
using a resist pattern
113
as a mask. Thus, it is impossible to reduce the size of the contact holes
114
, in which the source/drain contacts should be formed, to less than the minimum opening size of the resist
Chaudhuri Olik
Matsushita Electric - Industrial Co., Ltd.
Nixon & Peabody LLP
Pham Hoai
Studebaker Donald R.
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