Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Assembly of plural semiconductive substrates each possessing...
Reexamination Certificate
2002-04-24
2003-05-06
Lebentritt, Michael S. (Department: 2824)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Assembly of plural semiconductive substrates each possessing...
C438S106000, C438S959000, C438S978000, C438S108000, C257S676000, C257S777000, C257S778000
Reexamination Certificate
active
06558977
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device in which a second semiconductor chip is disposed on and connected to a first semiconductor chip and a method for fabricating the same.
As recent electronic equipment has become smaller in size and higher in processing speed, a wide range of study has been conducted on a three-dimensional device structure composed of two or more types of semiconductor chips stacked in layers. Compared with technology for forming a three-dimensional device, technology for individually packaging two or more types of semiconductor chips has advantages or disadvantages depending on the types of semiconductor elements provided in the semiconductor chips. For example, individual packaging of semiconductor elements formed by a merging process such as a merged memory-logic device complicates the process, resulting in higher cost. To reduce cost, there have been proposed various methods in each of which two types of semiconductor chips having semiconductor elements formed individually by appropriate processes are stacked in layers. Some of such devices are already being commercialized.
A description will be given herein below to a structure of a conventional three-dimensional semiconductor device and a fabrication method therefor.
FIG. 17
is a cross-sectional view showing the structure of the conventional three-dimensional device.
FIGS. 18A
to
18
C are cross-sectional views illustrating the process steps for fabricating the conventional three-dimensional device.
As shown in
FIG. 17
, the conventional three-dimensional device comprises: a first semiconductor chip
110
having a plurality of first internal electrodes
111
and bonding pads
112
each disposed on an upper surface thereof; a second semiconductor chip
120
having a plurality of second internal electrodes
121
disposed on an upper surface thereof; a die pad
131
for carrying the first semiconductor chip
110
; and leads
132
for transmitting electric signals between external equipment and respective elements such as transistors within the semiconductor chips
110
and
120
.
The second semiconductor chip
120
is mounted on the first semiconductor chip
110
with the second internal electrodes
121
aligned with respect to the first internal electrodes
111
. The first and second internal electrodes
111
and
121
are electrically connected to each other via metal bumps
123
. A resin
130
is filled in the space between the first and second semiconductor chips
110
and
120
to provide adhesion therebetween, thereby integrating the first and second semiconductor chip
110
and
120
into a single device. The die pad
131
and the leads
132
have been cut off from a single lead frame. The first semiconductor chip
110
has been secured to the die pad
131
by using a conductive paste
133
containing a metal such as Pd or Ag. The bonding pads
112
of the first semiconductor chip
110
and the leads
132
are electrically connected via bonding wires
134
. The first semiconductor chip
110
, the second semiconductor chip
120
, the bonding wires
134
, the die pad
131
, and the leads
132
are sealed with a sealing resin
135
to be packaged.
A description will be given next to a method for fabricating the conventional semiconductor device.
In the step shown in
FIG. 18A
, the first and second semiconductor chips
110
and
120
are aligned by the following procedure. First, the first semiconductor chip
110
having the plurality of first internal electrodes
111
on the upper surface thereof is prepared and placed on a mounting jig (not shown). Then, the resin
130
is applied to the upper surface of the first semiconductor chip
110
. On the other hand, the second semiconductor chip
120
having the plurality of second internal electrodes
121
on the upper surface thereof and barrier metals
122
over the upper surface is prepared. Then, the metal bumps
123
are formed on the barrier metals
122
of the second semiconductor chip
120
. Subsequently, the second internal electrodes
121
(barrier metals
122
) are aligned with respect to the first internal electrodes
111
by opposing, from above, the second semiconductor chip
120
to the first semiconductor chip
110
with the lower surface of the second semiconductor chip
120
facing downward.
Next, in the step shown in
FIG. 18B
, the first and second semiconductor chips
110
and
120
are bonded to each other by the following procedure. First, the second semiconductor chip
120
is heated and pressed from the back surface thereof by using a metal tool
140
so that the first internal electrodes
111
of the first semiconductor chip
110
and the second internal electrodes
121
of the second semiconductor chip
120
are bonded to each other via the metal bumps
123
formed on the second internal electrodes
121
(on the barrier metals
122
) of the second semiconductor chip
120
. After bonding, the resin
130
filled in the space between the two semiconductor chips
110
and
120
is cured under the irradiation of UV light
141
or by heating.
Next, in the step shown in
FIG. 18C
, a wire bonding step is performed with respect to the bonded and integrated semiconductor chip. First, a lead frame
137
having the die pad
131
and the leads
132
is prepared. Then, the first semiconductor chip
110
is secured onto the die pad
131
by using the conductive paste
133
containing Pd, Ag, or the like. Subsequently, the bonding pads
112
of the first semiconductor chip
110
and the leads
132
of the lead frame
137
are connected with the bonding wires
134
.
Next, in the step shown in
FIG. 18D
, the wire bonded semiconductor device is packaged by the following procedure. First, the first semiconductor chip
110
, the second semiconductor chip
120
, the bonding wires
134
, the die pad
131
, and the leads
132
are sealed with the sealing resin
135
. At this time, the lower or outer side surfaces of the leads
132
are uncovered with the sealing resin
135
and exposed such that the exposed portions function as external terminals.
By the foregoing steps, the three-dimensional device composed of the second semiconductor chip
120
mounted on and integrated with the first semiconductor chip
110
is formed.
However, the semiconductor device as the three-dimensional device has the following problems.
Since the second semiconductor chip
120
bonded onto the first semiconductor chip
110
by face-down bonding has been cut out of a wafer by dicing, the corners
145
of the lower surface of the second semiconductor chip
120
that have been ground during dicing remain unchanged. As a result, a stress occurring during the curing of the sealing resin is localized to the corners
145
of the lower surface of the second semiconductor chip
120
so that the overall characteristics of the semiconductor device are more likely to deteriorate.
Even if the semiconductor device is not sealed with a sealing resin, the reliability of connection between the semiconductor chips is more likely to lower under the influence of the warping of the semiconductor chips when the semiconductor device is heated.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a semiconductor device and a fabrication method therefor which suppress the localization of a stress to the corners of the back surface of the second semiconductor chip bonded to the first semiconductor chip or reduces the warping of the chips.
A first semiconductor device of the present invention comprises: a first semiconductor chip having a first electrode disposed on an upper surface thereof; and a second semiconductor chip having a second electrode disposed on an upper surface thereof, the second semiconductor chip being mounted on the first semiconductor chip with the second electrode being electrically connected to the first electrode, a corner of a lower surface of the second semiconductor chip being blunted by processing.
The arrangement suppresses the localization of the stress to the corner of the lower surfac
Kaneko Hideyuki
Matsumura Kazuhiko
Nagao Koichi
Nakaoka Yukiko
Lebentritt Michael S.
Luhrs Michael K.
Matsushita Electric - Industrial Co., Ltd.
Nixon & Peabody LLP
Studebaker Donald R.
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