Semiconductor device manufacturing: process – Chemical etching
Reexamination Certificate
2000-09-29
2003-09-23
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Chemical etching
C438S003000, C438S006000, C438S239000, C438S243000, C438S250000, C438S694000, C438S695000, C438S697000, C438S306000
Reexamination Certificate
active
06624076
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention generally relates to a semiconductor device and a method for fabricating the device. More particularly, the present invention relates to a semiconductor device, in which an electronic device has been formed out of a multilayer structure, including a ferroelectric film, on an insulating film deposited over a pattern of electrodes or interconnects, and to a method for fabricating the device.
An electronic device formed out of a multilayer structure including a ferroelectric film, e.g., a ferroelectric capacitor including a capacitive insulating film made of a ferroelectric material, not only has a high dielectric constant but also shows hysteresis with residual electric polarization. Accordingly, in the fields of capacitors with large capacitance and nonvolatile memories, those capacitors including a ferroelectric film have recently been replacing the known capacitors including a capacitive insulating film of silicon dioxide or silicon nitride.
Hereinafter, a known method for fabricating a semiconductor device (which will be herein called a “first prior art example” for convenience sake) will be described with reference to FIGS.
8
(
a
) through
8
(
e
).
First, as shown in FIG.
8
(
a
), an interconnect (or gate electrode)
11
of polysilicon with a thickness of 400 nm, for example, is formed on a semiconductor substrate
10
, in which a diffused layer for an MOS transistor, for example, has been defined. Next, a silicon nitride film
12
is deposited to a thickness of 40 nm, for example, over the entire surface of the substrate
10
as well as over the interconnect
11
. Then, an interlayer dielectric film
13
, which may be a first silicon dioxide film doped with boron and phosphorus, is deposited to a thickness of 1000 nm, for example, over the silicon nitride film
12
.
Subsequently, as shown in FIG.
8
(
b
), a resist film
14
is deposited on the interlayer dielectric film
13
so that the surface of the film
14
becomes as flat as possible. Then, the resist film
14
and interlayer dielectric film
13
are etched back, thereby planarizing the surface of the interlayer dielectric film
13
as shown in FIG.
8
(
c
).
Thereafter, as shown in FIG.
8
(
d
), first metal film
14
, ferroelectric film
15
and second metal film
16
are deposited in this order on the interlayer dielectric film
13
with the planarized surface. In this case, the first and second metal films
14
and
16
may be both made of platinum. Examples of known techniques for depositing the ferroelectric film
15
include sputtering, metalorganic chemical vapor deposition (MOCVD) and spin coating. Among these techniques, the spin coating technique is advantageous in uniformity of film thickness and quality, stability of conditions and productivity. In a spin coating process, the ferroelectric film
15
is formed by coating the surface of an underlying layer with an organometallic solution, containing the constituent metal of the ferroelectric film
15
, using a coater, and then annealing and crystallizing the resultant coating at an elevated temperature. In this process, the coating is formed using a coater. Thus, the thickness of the resultant ferroelectric film
15
is much affected by the unevenness of the underlying layer. Specifically, part of the ferroelectric film
15
, covering the upper corners of a stepped portion, will be relatively thin, while another part of the ferroelectric film
15
, covering the lower corners of the stepped portion will be relatively thick. Accordingly, to uniformize the thickness of the ferroelectric film
15
, the surface of the interlayer dielectric film
13
should be as flat as possible.
Next, as shown in FIG.
8
(
e
), the second metal film
16
, ferroelectric film
15
and first metal film
14
are dry-etched and patterned in this order, thereby forming a capacitor made up of upper electrode
16
A, capacitive insulating film
15
A and lower electrode
14
A. In this step, parts of the interlayer dielectric film
13
, on which the capacitor does not exist, is over-etched through the dry etching process. As a result, a patterned interlayer dielectric film
13
A is obtained.
Subsequently, although not shown, a second silicon dioxide film is deposited to a thickness of 200 nm, for example, over the entire surface of the semiconductor substrate
10
as well as over the respective regions where the MOS transistor and the capacitor will be formed. Then, a contact hole is opened through respective parts of the second silicon dioxide film and the patterned interlayer dielectric film
13
A, in which the MOS transistor will be formed. Thereafter, the contact hole is filled in with a conductor film, thereby forming a contact connected to the MOS transistor.
The multilayer structure, consisting of the second metal film
16
, ferroelectric film
15
and first metal film
14
, includes the ferroelectric film
15
, which is dry-etched at a low rate because the film
15
contains a metal that has a high melting point. Accordingly, the multilayer structure is also dry-etched at a relatively low rate. In other words, the dry-etch selectivity of the multilayer structure to the interlayer dielectric film
13
becomes low.
Thus, in the dry etching process for forming a capacitor made up of the upper electrode
16
A, capacitive insulating film
15
A and lower electrode
14
A, the interlayer dielectric film
13
is over-etched so deep, except for its part on which the capacitor will be formed. As a result, the interconnect
11
is also partially etched away unintentionally as shown in FIG.
8
(
e
). Particularly if some dopants such as boron and phosphorus have been added to the silicon dioxide film to further planarize the interlayer dielectric film
13
by a reflow process, the dry-etch rate of the interlayer dielectric film
13
will further increase. That is to say, the etch selectivity of the multilayer structure to the interlayer dielectric film
13
will further decrease in that case. Consequently, the above problem will get even more noticeable.
To solve such a problem, an alternative method for fabricating a semiconductor device (which will herein be called a “second prior art example” for convenience sake) was suggested. Hereinafter, this method will be briefly described with reference to FIGS.
9
(
a
) through
9
(
c
).
Specifically, a relatively thick interlayer dielectric film
13
, which is a silicon dioxide film containing boron and phosphorus, is deposited to a thickness of about 1500 nm, for example, over the silicon nitride film
12
and then has its surface planarized as shown in FIG.
9
(
a
). Next, as shown in FIG.
9
(
b
), the first metal film
14
, ferroelectric film
15
and second metal film
16
are deposited in this order on the interlayer dielectric film
13
with the planarized surface. Then, the second metal film
16
, ferroelectric film
15
and first metal film
14
are dry-etched and patterned in this order, thereby forming a capacitor consisting of the upper electrode
16
A, capacitive insulating film
15
A and lower electrode
14
A as shown in FIG.
9
(
c
). According to this alternative method, the interlayer dielectric film
13
also has its thickness reduced or over-etched, except for its part on which the capacitor will be formed, during the dry etching process. As a result, a patterned interlayer dielectric film
13
B is obtained.
In this second prior art example, however, the interlayer dielectric film
13
is relatively thick, so is the patterned interlayer dielectric film
13
B. Thus, a contact hole to be formed in that interlayer dielectric film
13
B will have a greater aspect ratio. In that case, the metal film to fill the contact hole will have decreased step coverage, i.e., the contact hole cannot be covered with a metal film satisfactorily. As a result, problems of different types, e.g., disconnection or increase in contact resistance, newly arise. Accordingly, it is not preferable to increase the thickness of the interlayer dielectric film
13
excessively.
SUMMARY OF THE INVENTION
It is
Lee Granvill D
Smith Matthew
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