Semiconductor device manufacturing: process – Forming bipolar transistor by formation or alteration of... – Including isolation structure
Reexamination Certificate
2000-03-21
2002-12-03
Thomas, Tom (Department: 2811)
Semiconductor device manufacturing: process
Forming bipolar transistor by formation or alteration of...
Including isolation structure
C438S341000
Reexamination Certificate
active
06489212
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a semiconductor device suitable for fast operation, and a method for fabricating the same.
2. Background of the Related Art
In general, a high speed operation of a device is most important for a high frequency semiconductor circuit. Higher operating speeds are possible as device size is reduced. But there are operational problems associated with reduced device size. To solve this, a related art suppresses ajunction capacitance between a base and a collector using selective epitaxial layer growth and a floating poly base, plus a thick insulating film is provided on a bottom of the floating poly base for reduction of a parasitic capacitance.
A related art method for fabricating a semiconductor device will be explained with reference to the attached drawings. FIGS.
1
A~
1
I illustrate sections showing the steps of a related art method for fabricating a semiconductor device.
Referring to
FIG. 1A
, the related art method for fabricating a semiconductor device starts with selective implantation, and drive diffusing, of N
+
impurity ions into an entire surface of a P type semiconductor substrate
11
, to form a heavily doped N type well region
12
in the surface of the semiconductor substrate
11
. A CVD (Chemical Vapor Deposition) oxide film
13
is formed on an entire surface of the semiconductor substrate
11
inclusive of the heavily doped N type well region
12
. A first polysilicon layer
14
is deposited on the CVD oxide film
13
for use as a floating base, and subjected to pattering by photolithography and etching. As shown in FIG.
1
B, a first insulating film
15
is formed on an entire surface of the semiconductor substrate
11
inclusive of the first polysilicon layer
14
. Then, the first insulating film
15
, the first polysilicon layer
14
and the CVD oxide film
13
are selectively removed to form a hole
27
that exposes a portion of the N type well region
12
. The remaining CVD oxide film
13
is used for isolation of devices, and surfaces of the N type well region
12
on both sides of the CVD oxide film
13
at a center portion thereof are exposed.
As shown in
FIG. 1C
, a second insulating film is formed in the contact hole
27
and subjected to etch back to form second insulating sidewalls
16
at edges of the first insulating film
15
, the first polysilicon layer
14
, and the CVD oxide film
13
. The exposed semiconductor substrate
11
is used as seeds in making an epitaxial growth to form a lightly doped n type first epitaxial layer
17
on the surface of the semiconductor substrate
11
. The epitaxial growth using the semiconductor substrate as seeds changes the surface of the semiconductor substrate into a projected form, with a lightly doped n type epitaxial layer
17
grown on the surface.
As shown in
FIG. 1D
, the second insulating film sidewalls
16
at edges of the first insulating film
15
and the first polysilicon layer
14
are selectively removed. As shown in
FIG. 1E
, the first polysilicon layer
14
and the first epitaxial layer
17
are used as seeds in making an epitaxial growth of the semiconductor substrate
11
in vertical and horizontal directions, to grow a P type second epitaxial layer
18
.
As shown in
FIG. 1F
, impurity ions are selectively implanted into the second epitaxial layer
18
, to form a P type base region
19
and an N
+
collector contact region
20
, respectively. Then, a thermal oxidation is conducted, to form a third insulating film
21
on surfaces of the P type base region
19
and the N
+
collector contact region
20
.
As shown in
FIG. 1G
, a fourth insulating film is formed on the exposed surfaces of the structure of
FIG. 1F
, and etched back to form fourth insulating film sidewalls
22
at both edges of the first insulating film
15
while exposing a portion of the underlying base region
19
. In this instance, the fourth insulating film is overetched to expose the surface of the base region
19
by also selectively removing a portion of the third insulating film
21
formed on a surface of the base region
19
. The fourth insulating film sidewalls
22
are used to form an emitter in the base region
19
in a self-aligned manner, as follows.
As shown in
FIG. 1H
, the fourth insulating film sidewalls
22
and the first insulating film
15
are used as masks to self-align the implementation of N
+
impurity ions, and so form an N
+
emitter region
23
in a surface of the base region
19
, i.e., a first intermediate structure. Then, a second polysilicon layer
24
is deposited on the exposed surfaces of the first intermediate structure, and subjected to photolithography and etching to selectively leave the second polysilicon layer
24
only on the emitter region
23
, the N+ collector region
20
and the first insulating film
15
adjacent thereto. As shown in
FIG. 1I
, a general metal wiring is formed on the intermediate structure of
FIG. 1H
, to form metal wiring
25
on the semiconductor substrate
11
, thereby completing the related art fabrication process. The metal wiring
25
is formed to connect the second polysilicon layer
24
to the first polysilicon layer
14
.
However, the related art method for fabricating a semiconductor device has a problem in that the thick oxide film
13
on the bottom of the floating poly base
14
results in the thick N-epitaxial layer
17
(over 1 &mgr;m) that affects the maximum speed that the device can operate. That is, the excessively thick N-epitaxial layer
17
deteriorates the maximum speed of operation under low voltage conditions.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a semiconductor device and a method for fabricating the same that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide a semiconductor device and a method for fabricating the same, which operates well operative at a high speed.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present to invention, as embodied and broadly described, a semiconductor device is provided that includes a semiconductor substrate, an insulating film formed discontinuously on the semiconductor substrate so as to leave at least one gap where the semiconductor substrate is exposed, the insulating film having first portions below a surface of the semiconductor substrate and second portions above the surface of the semiconductor substrate, respectively, and a semiconductor layer formed on the semiconductor substrate at one of the at least one gap in said insulation film, a height of said semiconductor layer being equal to a height of the insulating film.
In other aspect of the present invention, there is provided a method for fabricating a semiconductor device. Such a method comprises oxidizing a substrate to form an insulating film having at least one gap where the substrate is exposed, and forming a semiconductor layer on the substrate at one of the at least one gap in the insulating film, a height of the semiconductor layer being equal to a height of the insulating film.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 4851362 (1989-07-01), Suzuki
patent: 5017503 (1991-05-01), Shiba
patent: 6060365 (2000-05-01), Kim
Birch & Stewart Kolasch & Birch, LLP
Hynix / Semiconductor Inc.
Kang Donghee
Thomas Tom
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