Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Including adhesive bonding step
Reexamination Certificate
2001-07-31
2004-10-26
Flynn, Nathan J. (Department: 2826)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Including adhesive bonding step
C257S737000, C257S750000, C257S758000, C257S738000, C257S757000, C257S751000, C257S752000, C438S117000, C438S119000, C438S120000, C438S121000
Reexamination Certificate
active
06808962
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device comprising semiconductor chips and a wiring layer, and a method for fabricating the semiconductor device.
2. Description of the Prior Art
Recently, the tendency that electronic equipments have higher performance, and are lighter, thinner, shorter and more down-sized makes semiconductor devices higher integrated, more functional and more down-sized as seen typically in ASIC of LSI.
Conventionally, wafers which have been processed are back-polished, and then diced and cut into respective pellets (also called semiconductor chips or semiconductor elements). Then, die bonding, wire bonding, resin sealing, etc. are performed on the respective pellets, and semiconductor devices are fabricated. The wire bonding electrically connects the semiconductor chips to lead frames.
For high-speed signal processing, semiconductor chips are recently flip chip bonded by using bumps.
The flip chip bonding may be performed by a method of bare chip mounting for mounting semiconductor chips on a print substrate as they are. However, in this method, it is difficult to handle the semiconductor chips. In consideration of retaining reliability, packaged semiconductor chips with bumps are used.
Recently, as a method for fabricating semiconductor devices comprising packaged semiconductor chips with bumps a method in which wiring, external terminals (metal posts), resin seal and bumps are formed on the wafer level, and the wafer is cut into respective semiconductor chips, and the respective semiconductor chips are packaged into CSP (Chip Scale Package) (Chip Scale International 99SEMI 1999) is proposed.
The thus prepared CSP is also called wafer level CSP.
Such semiconductor fabrication is called here wafer level semiconductor fabrication.
A partial section of such semiconductor device is shown in FIG.
9
. In
FIG. 9
, reference number
110
represents semiconductor chips (also called simply chips); reference number
115
represents an electrode (also called a terminal), reference number
120
represents an SiN passivation; reference number
125
represents a polyimide layer; a reference number
130
represents a wiring layer; reference number
131
represents a seed metal layer; reference number
132
represents an electrolytic plated copper layer; reference number
140
represents a resin seal layer (epoxy resin layer); reference number
150
represents a metal post; reference number
160
represents a barrier metal; and reference number
170
represents a solder ball.
In
FIG. 9
, the terminals
115
of the semiconductor chips
110
are connected to the wiring layer
130
formed on the surfaces of the semiconductor chips
110
. The wiring layer
130
is connected to the external terminals (called also the metal posts)
150
. The external terminals (metal posts)
150
are connected to the solder bumps
170
via the barrier metal layer
160
. A print circuit board is to be soldered by the solder balls
170
as bumps. The form of such semiconductor device, in which the semiconductor chips are mounted on the print circuit board, is similar to the conventional flip chip bonding for mounting semiconductor chips on print substrates.
The seal layer
140
is provided, burying the metal posts
150
.
In
FIG. 9
, the metal posts
150
structurally requires a diameter (100-200 &mgr;m) or about ⅔× a diameter of the solder balls
170
, and has an about 100 &mgr;m-height. The metal posts
150
are thick and have high rigidity.
Accordingly, when such semiconductor device mounted on a print circuit board is repeatedly subjected to temperature changes, thermal distortions take place due to thermal expansion coefficients difference (&Dgr;&agr;) between the respective semiconductor chips and the mounted print circuit board takes place, and cracks occur in the semiconductor chips
110
below the metal posts
150
.
The resin seal layer
140
is provided only on a surfaces of the semiconductor chips
110
where the wiring layer
130
is formed, which permits warps to occur. Accordingly, problems of poor flatness of the solder balls
170
and low mounting yields occur.
SUMMARY OF THE INVENTION
In view of the above-described problems, the present invention was made, and an object of the present invention is to provide a semiconductor device which does not permit cracks and warps to occur in semiconductor chips mounted on a substrate even when subjected to temperature changes, and which has accordingly high yields, and a method for fabricating the semiconductor device.
The present invention is a semiconductor device comprising a semiconductor chip having electrodes; an insulation layer formed on a surface of the semiconductor chip where the electrodes of the semiconductor chip are formed; and a wiring layer formed on the insulation layer, the electrodes of the semiconductor chip and the wiring layer being connected to each other via connection members disposed in the insulation layer.
The present invention is the semiconductor device wherein the connection members include wire bumps disposed on the electrodes of the semiconductor chip.
The present invention is the semiconductor wherein the connection members further include cured conductive pastes formed on the wire bumps.
The present invention is the semiconductor device wherein the connection members include a metal layer formed on the electrodes of the semiconductor chip, and cured conductive pastes disposed on the metal layer.
The present invention is the semiconductor device comprising a solder resist layer having openings, for covering the wiring layer, solder balls disposed in the openings of the solder resist layer, connected to the wiring layer.
The present invention is the semiconductor device wherein an additional insulation layer is formed on a surface of the semiconductor chip, which is opposite to the surface where the electrodes are formed.
The present invention is a method for fabricating a semiconductor device comprising the steps of preparing a wafer including a plurality of semiconductor chips with electrodes formed on; forming connection members on the electrodes of the respective semiconductor chips; forming an insulation layer in a thickness to cover the connection members on the surfaces of the respective semiconductor chips where the electrodes of the semiconductor chips are formed; polishing the insulation layer to expose the connection members;
forming an electroless plated layer on the insulation layer; and forming, with the electroless plated layer as a feeder layer of electric current, an electrolytic plated layer on the electroless plated layer selectively only in regions for a wiring layer; etching off the electroless plated layer except regions of the electroless plated layer corresponding to the electrolytic plated layer to form the wiring layer including the electroless plated layer and the electrolytic plated layer; and severing the wafer into the respective semiconductor chips to fabricate the semiconductor device.
The present invention is the method for fabricating a semiconductor device further comprising the steps of forming a solder resist layer having openings on the wiring layer; and forming solder balls in the openings of the solder resist layer, connected to the wiring layer.
The present invention is the method for fabricating a semiconductor device wherein the connection members are formed by forming wire bumps on the electrodes of the semiconductor chips by wire bonding.
The present invention is the method for fabricating a semiconductor device wherein the connection members are formed by forming cured conductive pastes on the wire bumps.
The present invention is the method for fabricating a semiconductor device wherein the connection members are formed on the electrodes of the semiconductor chips by forming a metal layer by sputtering and forming cured conductive pastes on the metal layer.
The present invention is the method for fabricating a semiconductor device wherein in the step of forming an electrolytic pl
Dai Nippon Printing Co. Ltd.
Erdem Fazli
Flynn Nathan J.
Parkhurst & Wendel L.L.P.
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