Active solid-state devices (e.g. – transistors – solid-state diode – Heterojunction device – Bipolar transistor
Reexamination Certificate
1999-07-01
2001-10-30
Thomas, Tom (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Heterojunction device
Bipolar transistor
C257S198000, C257S586000, C257S565000, C257S571000, C438S235000, C438S309000, C438S312000, C438S317000
Reexamination Certificate
active
06310368
ABSTRACT:
BACKGROUND OF THE INVENTION
1. FIELD OF THE INVENTION
The present invention relates to a method for fabricating a semiconductor device, more particularly, to a method for forming interconnections. The present invention also relates to a semiconductor device having interconnections formed by the above method.
2. DESCRIPTION OF THE RELATED ART
In recent years, in order to realize high integration of hetero-junction bipolar transistors (HBTs), a reduction in the size of HBTs has become requisite. In particular, a method for fabrication of HBTs which can realize a reduction in the size of base mesas and self-aligned formation of base electrodes has been required.
Hereinbelow, as one conventional method for fabricating a semiconductor device, a fabrication process disclosed in Japanese Laid-Open Publication No. 6-69223 will be described with reference to
FIGS. 3A
to
3
D.
Referring to
FIG. 3A
, an i-type GaAs buffer layer
302
, an n
+
-type GaAs sub-collector layer
303
, an n-type GaAs collector layer
304
, a p
+
-type GaAs base layer
305
, an n-type AlGaAs emitter layer
306
, a graded layer
307
made of n-type InGaAlAs and the like, and an n
+
-type InGaAs cap layer
308
are sequentially formed by epitaxial growth on a semi-insulating GaAs substrate
301
. Then, a conductive layer
309
for formation of an emitter electrode and an SiO
2
layer
310
are deposited on the cap layer
308
. A photoresist mask of a predetermined pattern is then formed on the resultant structure to pattern the conductive layer
309
and the SiO
2
layer
310
. Using the patterned conductive layer
309
and SiO
2
layer
310
as amask, the cap layer
308
, the graded layer
307
, and the emitter layer
306
are etched to form an emitter mesa with the base layer
305
being exposed on both sides of the emitter mesa.
Referring to
FIG. 3B
, a thick SiO
2
layer is formed to cover the entire surface of the resultant structure, and then partly removed by anisotropic etching to form side-wall type dummy bases
311
. Then, using the dummy bases
311
as a mask, the base layer
305
, the collector layer
304
, and a surface portion of the sub-collector layer
303
are partly removed by isotropic etching to form a base mesa. Subsequently, collector electrodes
312
are formed on the exposed surface of the sub-collector layer
303
on both sides of the base mesa by an appropriate method. Simultaneously with the formation of the collector electrodes
312
, a conductive layer, which is also denoted by
312
, is formed on the SiO
2
layer
310
located on the conductive layer
309
and the dummy bases
311
formed on both sides of the SiO
2
layer
310
.
A photoresist mask (not shown) of a predetermined pattern is then formed and used to remove regions of the sub-collector layer
303
and regions of the upper portion of the buffer layer
302
underlying peripheral portions of the collector electrodes
312
by etching, so as to form a collector mesa.
Referring to
FIG. 3C
, a planarizing insulating film
313
made of polyimide is applied to the resultant structure so as to cover the collector mesa formed in the above step, to planarize the resultant structure. Then, the surface portion of the planarizing insulating film
313
in the vicinity of the emitter mesa is etched back to a position near the base layer
305
.
Referring to
FIG. 3D
, the dummy base
311
is then removed by a treatment with hydrofluoric acid and the like. Subsequently, a photoresist mask
314
of a predetermined pattern is formed, and then conductive layers
315
for formation of base electrodes is deposited. This deposition process allows for formation of the base electrodes
315
in a self-aligning manner with respect to the emitter electrode
309
(note that
FIG. 3D
shows an unfavorable example where the base electrodes
315
are disconnected, as will be described hereinafter).
Simultaneously with the formation of the conductive layers
315
, conductive layers
316
are also formed on the photoresist mask
314
. However, such unnecessary conductive layers
316
are lifted off when the photoresist mask
314
is removed. In this way, a basic structure of the HBT is completed.
Thus, the base mesa is formed in a self-aligning manner by using the side-wall type dummy bases
311
. In particular, the distance L between the edge of the top surface of the base mesa and the side wall of the emitter electrode
309
(see
FIG. 3B
) is controlled by the thickness of the SiO
2
film at the formation of the dummy bases
311
and the conditions of the dry etching. As a result, the size of the base mesa can be reduced compared with the case where the base mesa is formed by being patterned in a photolithographic process, and thus the parasitic capacitance at the base-collector junction can be greatly reduced.
However, the above conventional method using the dummy bases
311
has the following problems.
In order to facilitate the formation of interconnections extending from the base electrodes
315
, the base electrodes
315
need to be formed not only on the base layer
305
, but also continuously on the planarizing insulating film
313
located adjacent to the base layer
305
.
As described with reference to
FIG. 3C
, part of the planarizing insulating film
313
is etched back to a position near the base layer
305
. In this etch-back process, it is extremely difficult to stop the etching accurately and with good reproducibility, at the very moment when the base layer
305
is exposed. Moreover, partly because of uniformity of the planarizing insulating film
313
in the wafer plane, the above etch-back process results in forming a step H between the top surface of the base layer
305
and the top surface of the planarizing insulating film
313
. As a result, as shown in circled areas denoted by the reference numeral
317
in
FIG. 3D
, each base electrode
315
is formed over upper and lower surfaces having the step H therebetween. Furthermore, the recess portion formed by the steps H normally has an inverted tapered shape as shown in the circled areas
317
.
The thickness of the base electrodes
315
is typically set to be about 200 nm or less in order to prevent short-circuiting with the emitter electrode
309
. Accordingly, if the height of the step H between the top surface of the base layer
305
and the top surface of the planarizing insulating film
313
is greater than the thickness of the deposited conductive layer
315
, the portion of the conductive layer
315
formed on the base layer
305
and the portion of the conductive layer
315
formed on the planarizing insulating film
313
are separated from each other vertically, causing electric disconnection and thus reducing fabrication yield.
SUMMARY OF THE INVENTION
A semiconductor device of the present invention includes: a semiconductor layered structure including a predetermined mesa portion, formed on a semiconductor substrate; a support member formed so as to bury the mesa portion; and an interconnection layer formed on a top surface of the semiconductor layered structure so as to extend over a top surface of the support member. The interconnection layer is in contact with only a top surface of the mesa portion without being in contact with a bottom surface of the mesa portion. The top surface of the support member has a smoothed profile, and the top surface of the mesa portion and the smoothed top surface of the support member are in substantially the same plane.
In one embodiment, the support member is made of a material which is thermally deformable.
In another embodiment, the support member is made of a material which swells with a solvent.
In still another embodiment, the support member is made of polyimide.
For example, the top surface of the mesa portion may include a top surface of a base layer of the semiconductor layered structure, and the support member may include an insulating film.
A method for fabricating a semiconductor device according to the present invention includes the steps of: forming a semiconductor layered structure on a semiconductor sub
Kang Donghee
Nixon & Vanderhye P.C.
Sharp Kabushiki Kaisha
Thomas Tom
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