Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
2005-12-28
2008-03-25
Geyer, Scott B. (Department: 2812)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S074000, C438S404000, C438S481000, C438S570000, C257SE21564
Reexamination Certificate
active
07348255
ABSTRACT:
A semiconductor structure has an active region on a substrate, and recessed portions are formed at lower edges of lateral portions of the semiconductor structure. Patterned first insulation layers for device isolation are buried into the recessed portions. Second insulation layers for device isolation are formed on sidewalls of the first insulation layers.
REFERENCES:
patent: 6228691 (2001-05-01), Doyle
patent: 6919258 (2005-07-01), Grant et al.
patent: 7029964 (2006-04-01), Cheng et al.
Blakely & Sokoloff, Taylor & Zafman
Geyer Scott B.
Hynix / Semiconductor Inc.
Nikmanesh Seahvosh
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