Active solid-state devices (e.g. – transistors – solid-state diode – Thin active physical layer which is – Heterojunction
Reexamination Certificate
1997-09-02
2001-02-20
Crane, Sara (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Thin active physical layer which is
Heterojunction
C257S020000, C257S192000
Reexamination Certificate
active
06191432
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device having a fine structure, and in particular to a fine annular quantum wire structure which can be integrated, and a semiconductor device and a memory device using it.
Various semiconductor elements using silicon single crystals as a fundamental material are used widely and commonly. For enhancing the performance of these semiconductor elements, it is one of effective means to increase the transit speed (mobility) of electrons transiting in the material. The upper limit value of the mobility of electrons in single crystals is determined by physical property factors, and the upper limit value cannot be improved by the structure. In recent years, however, the fact that the mobility of electrons in a silicon crystal having strain is increased as compared with the original silicon crystal has been reported.
In a common method for fabricating such elements, a crystal slightly differing in lattice constant from the silicon crystal is prepared and thereon a silicon layer thinner than the critical film thickness is formed by using a thin film growing technique as means for providing the silicon crystal with a strain. To be concrete, a SiGe alloy crystal layer having a Ge composition of approximately 30% as an alloy crystal having lattice constants slightly greater than silicon is prepared, and thereon a silicon thin film layer having a thickness of 100 nm or less is formed. (In this case, lattice constants of the SiGe crystal are greater than those of the Si crystal by approximately 1.2%.) At this time, it is difficult to procure an inexpensive SiGe crystal substrate which is industrially mass-produced and which is excellent in quality. Usually, therefore, a silicon wafer is used as a substrate, and thereon SiGe having a sufficient thickness (thicker than the critical film thickness) is formed to obtain a crystal which is slightly greater in lattice constant than Si.
The Si layer thus formed is subjected to tensile strain. As a result, not only the mobility of electrons is improved, but also there is obtained such an advantage that the potential position of the conduction band is moved to a lower position as compared with the SiGe layer by the effect of the tensile strain and consequently electrons can be stored more easily. There is an example in which n-type MOSFETs and MODFETs were fabricated by way of trial by using such characteristics. On the other hand, for improving the mobility of holes, it is more advantageous to use a SiGe layer having compressive strain as compared with the Si layer having tensile strain fabricated as described above. In other words, a SiGe layer with no strain relaxation caused becomes necessary in this case.
For thus forming a p-type MOSFET (or MODFET) with a hole mobility increased by using the strain of a crystal, there is required a thin film layer structure (modulated dope structure) different from that in the case where the n-type MOSFET (MODFET) is formed. In other words, for forming a CMOS incorporating both an n-type FET and a p-type FET, layered structures suited for both the n-type FET and the p-type FET need to be formed separately. Therefore, conventional hetero devices had a big problem in integration.
In a quantum confined structure, electrons or holes are confined in an extremely small area in a semiconductor material (to be concrete, an area having dimensions shorter than the wavelength of electrons). Such a quantum confined structure has unique characteristics which cannot be obtained in conventional semiconductors. Therefore, its fabrication results by way of trial using various methods have been reported. Above all, a quantum well structure can be easily formed. In the case of the quantum well structure, a layer is formed from two kinds of semiconductors having different band gaps and quantum confinement is conducted in only one direction. A large number of examples of application thereof have been reported.
As for a quantum wire structure with quantum confinement conducted in two directions and a quantum box structure with quantum confinement conducted in all of three-dimensional directions, it is difficult to form them and reports of them are few.
BRIEF SUMMARY OF THE INVENTION
An object of the present invention is to provide a structure which allows a p-type MOSFET and an n-type MOSFET to be simultaneously formed by using a system increased in mobility by the effect of strain.
Another object of the present invention is provide a ring-shaped quantum wire structure formed by using an existing silicon process, and a semiconductor device using such a structure. To be concrete, a semiconductor device suitable for a change magnetic field measuring instrument and a high frequency modulator, and a memory device requiring no holding power are provided.
In accordance with the present invention, the following measures are taken.
In accordance with an essential aspect of the present invention, a layered structure of Si and SiGe incorporating a strain is formed, and thereafter there is formed a trench or a mesa, on which a gate oxide film is formed.
A semiconductor device according to a first aspect of the present invention is characterized by comprising a superlattice comprising a first semiconductor layer having a first band-gap, a second semiconductor layer having a band-gap narrower than the first band-gap, the superlattice having a band structure with an energy level of a conduction band of the second semiconductor layer being lower than an energy level of a conduction band of the first semiconductor layer and an energy level of a valence band of the second semiconductor layer being lower than an energy level of a valence band of the first semiconductor layer, or a band structure with an energy level of a conduction band of the second semiconductor layer being higher than an energy level of a conduction band of the first semiconductor layer and an energy level of a valence band of the second semiconductor layer being higher than an energy level of a valence band of the first semiconductor layer; an exposed face formed on an orientation different from an orientation on which the superlattice is formed, an end face of the superlattice being exposed to the exposed face; and a channel selectively formed on the exposed face. In other words, a semiconductor device according to the first aspect of the present invention has a superlattice structure called type II.
Preferred embodiments of a semiconductor device according to the present invention are as follows:
(1) A first field effect transistor having a channel formed by storing electrons in a semiconductor layer having a lower energy potential of a conduction band included in the first semiconductor layer and the second semiconductor layer forming the superlattice, and a second field effect transistor having a channel formed by storing holes in a semiconductor layer having a lower energy potential of a valence band included in the first semiconductor layer and the second semiconductor layer forming the superlattice are formed together.
(2) The first semiconductor layer comprises silicon, or an alloy crystal of silicon and germanium, and the second semiconductor layer comprises an alloy crystal of silicon and germanium having a higher germanium content ratio as compared with the first semiconductor layer, or germanium.
(3) The first semiconductor layer comprises silicon, or an alloy crystal of silicon and germanium, the silicon or an alloy crystal of silicon and germanium containing a tensile strain, and the second semiconductor layer comprises an alloy crystal of silicon and germanium having a higher germanium content ratio as compared with the first semiconductor layer, or germanium, the alloy crystal of silicon and germanium, or germanium containing a compressive strain.
(4) A device further comprises a first electrode disposed on one end of the channel of the exposed face, and a second electrode disposed on the other end of the channel of the exposed face.
According to the first aspect of the present invention,
Kurobe Atsushi
Sugiyama Naoharu
Crane Sara
Kabushiki Kaisha Toshiba
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
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