Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Reexamination Certificate
1998-06-12
2001-04-24
Everhart, Caridad (Department: 2825)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
C257S740000, C438S621000, C438S653000, C438S906000
Reexamination Certificate
active
06222267
ABSTRACT:
This application is based on Japanese Patent Application No.
9-160119
filed on Jun. 17, 1997, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
a) Field of the Invention
The present invention relates to a semiconductor device and its manufacture method, and more particularly to a semiconductor device and its manufacture method capable of providing a low contact resistance between impurity doped regions in a surface layer of a silicon substrate and a wiring layer.
b) Description of the Related Art
A region heavily doped with impurities in the surface layer of a silicon substrate is electrically connected to a wiring layer of Al or Al alloy formed thereon by inserting a barrier metal layer therebetween for blocking solid diffusion of atoms in the substrate and in the wiring layer. The barrier metal layer improves the reliability of the contact area.
Known barrier metal materials are refractory metal silicide such as WSi
2
and MoSi
2
and refractory metal alloy such as TiW. In order to improve thermal endurance and barrier performance, a lamination structure of a refractory metal layer and a refractory metal nitride layer such as a lamination structure of TiN and Ti, and a lamination structure of HfN and Ti, has been recently used.
A contact resistance between a metal wiring layer and a semiconductor substrate depends on an impurity concentration of the semiconductor substrate and a work function of the metal. A contact resistivity &rgr;
c
is given by:
&rgr;
c
=C×exp
(4&pgr;(&egr;
s
m
*
)
½
/(
qh
)×(&phgr;
B
/N
D
) (1)
where &phgr;
B
is a Schottky barrier height at an interface between semiconductor and metal, N
D
is an impurity concentration of a semiconductor substrate, m
*
is an effective mass of carriers in the semiconductor substrate, &egr;
s
is a dielectric constant of semiconductor material, q is an electronic charge, h is a Planck's constant, and C is a constant.
As seen from the equation (1), the contact resistance can be lowered by increasing the impurity concentration N
D
. However, impurities near a limit of solid solubility are doped presently and it is difficult to increase the impurity concentration higher than the present level.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a semiconductor device and a manufacture method thereof capable of lowering a contact resistance between impurity doped regions of a silicon substrate and a metal wiring layer.
According to one aspect of the present invention, there is provided a semiconductor device comprising:
a silicon substrate; a plurality of impurity doped regions formed in a surface layer of the silicon substrate; contact layers each in contact with a surface of associated one of the plurality of impurity doped regions, the contact layer being made of an alloy selected from a group consisting of TiMo, TiNb, TiV, TiW, TiMoNb, TiMoTa, TiMoV, TiMoW, TiNbTa, TiNbV, TiNbW, TiMoNbTa, TiMoNbV, TiMoNbW, TiMoTaW, TiMoVW, TiNbTaW, TiNbVW, TiMoNbTaW, TiMoNbVW, ZrNb, ZrNbTa, HfNb, HfNbTa, TiZrNbTa, TiHfNb, TiHfNbTa, TiZrHfNb, TiZrHfNbTa, TiTa, ZrTa, HfTa, TiZrTa, TiHfTa, and TiZrHfTa; barrier layers each disposed on associated one of the contact layers and made of refractory metal nitride or refractory metal oxynitride; and a metal wiring layer disposed on each of the barrier layers.
According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device comprising the steps of: forming n-type impurity doped regions and p-type impurity doped regions in a surface layer of a silicon substrate; depositing an interlayer insulating film on the silicon substrate; forming contact holes through the interlayer insulating film, each of the contact holes exposing a partial surface of one of the n-type impurity doped regions and the p-type impurity doped regions; forming a contact layer on inner walls of the contact holes and on a surface of the interlayer insulating film, the contact layer being made of an alloy selected from a group consisting of TiMo, TiNb, TiV, TiW, TiMoNb, TiMoTa, TiMoV, TiMoW, TiNbTa, TiNbV, TiNbW, TiMoNbTa, TiMoNbV, TiMoNbW, TiMoTaW, TiMoVW, TiNbTaW, TiNbVW, TiMoNbTaW, TiMoNbVW, ZrNb, ZrNbTa, HfNb, HfNbTa, TiZrNbTa, TiHfNb, TiHfNbTa, TiZrHfNb, TiZrHfNbTa, TiTa, ZrTa, HfTa, TiZrTa, TiHfTa, and TiZrHfTa; forming a barrier layer made of metal nitride or metal oxynitride on a surface of the contact layer, by nitriding a surface layer of the contact layer in a nitrogen atmosphere or by oxynitriding a surface layer of the contact layer in an atmosphere containing oxygen and nitrogen; and forming a metal wiring layer on the barrier layer.
According to a further aspect of the present invention, there is provided a method of manufacturing a semiconductor device comprising the steps of: forming n-type impurity doped regions and p-type impurity doped regions in a surface layer of a silicon substrate; depositing an interlayer insulating film on the silicon substrate; forming contact holes through the interlayer insulating film, each of the contact holes exposing a partial surface of associated one of the n-type impurity doped regions and the p-type impurity doped regions; forming a contact layer on inner walls of the contact holes and on a surface of the interlayer insulating film, the contact layer being made through sputtering by using as a target an alloy selected from a group consisting of TiMo, TiNb, TiV, TiW, TiMoNb, TiMoTa, TiMoV, TiMoW, TiNbTa, TiNbV, TiNbW, TiMoNbTa, TiMoNbV, TiMoNbW, TiMoTaW, TiMoVW, TiNbTaW, TiNbVW, TiMoNbTaW, TiMoNbVW, ZrNb, ZrNbTa, HfNb, HfNbTa, TiZrNbTa, TiHfNb, TiHfNbTa, TiZrHfNb, TiZrHfNbTa, TiTa, ZrTa, HfTa, TiZrTa, TiHfTa, and TiZrHfTa, and by using as a sputtering gas a rare gas; and succeedingly after the contact layer forming step, depositing a barrier layer of nitride or oxynitride of the alloy on the contact layer, by reactive sputtering using as a sputtering gas a gas containing at least nitrogen gas, or a gas containing a nitrogen gas and an oxygen gas.
The contact layer is made of an alloy of a metal having a standard heat of formation larger than that of Si and a metal having a standard heat of formation smaller than that of Si. By adjusting the composition of the alloy, the Schottky barriers at interfaces between the contact layers and n-type and p-type impurity doped regions in the surface layer of the silicon substrate can be controlled to have desired values. It can therefore balance the contact resistances of both the n-type and p-type regions.
Since the metal element having a standard heat of formation larger than that of Si reduces a natural oxide film formed on the surface of a silicon substrate, an increase in the contact resistance to be caused by a presence of the natural oxide film can be suppressed.
As above, the contact resistance between an impurity doped region and a wiring layer can be lowered by contacting an alloy made of a combination of a metal having a standard heat of formation larger than Si and a metal having a standard heat of formation smaller than Si, to the impurity doped regions in the surface area of the silicon substrate.
REFERENCES:
patent: 5094981 (1992-03-01), Chung et al.
patent: 5236868 (1993-08-01), Nulman
patent: 5421974 (1995-06-01), Witt
patent: 8-69980 (1996-03-01), None
Hiroshi Nishimura, et al. “Reliable Submicron Vias Using Aluminum Alloy High Temperature Sputter Filling” Proc. 8th International IEEE VLSI Multilevel Interconnect. Conf., Jun. 1991.
Everhart Caridad
Yamaha Corporation
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