Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Metallic housing or support
Reexamination Certificate
2003-01-28
2004-03-09
Zarneka, David A. (Department: 2827)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Metallic housing or support
C438S121000, C438S123000, C438S124000, C438S611000, C029S827000, C361S717000, C361S718000, C361S719000, C361S723000
Reexamination Certificate
active
06703261
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device and a method of manufacturing the same. Particularly, the invention is concerned with a technique which is effectively applicable to a manufacturing technique for a high frequency power amplifier (high frequency power amplifier module) for a base station in a radio communication system such as a cellular communication system.
SUMMARY OF THE INVENTION
In a radio communication system such as a cellular communication system, a portable telephone set (a portable terminal) is connected to a base station adjacent to a telephone network by a speaker's operation of the telephone set, then is connected successively to a single or plural base stations, and finally a portable terminal of the party being called is called (originating a call), thereafter the portable telephone set assumes a state which permits talking with the called party. In this case, the base station amplifies the received signal and transfers the thus-amplified signal. Such an amplification is performed by means of a high frequency power amplifier for a base station.
Having made studies about the cost reduction of a high frequency power amplifier for a base station, the present inventor reviewed a sealing structure (package structure) as a main cause of high cost.
FIGS. 28
to
39
illustrate a semiconductor device (hereinafter referred to as the “studied semiconductor device”) which the present inventor had studied prior to the present invention. The studied semiconductor device is a high frequency power amplifier (a high frequency power amplifier module).
FIG. 28
is a plan view of the studied semiconductor device,
FIG. 29
is a side view thereof,
FIG. 30
is a plan view thereof with a cap removed, and
FIG. 31
is a schematic sectional view of the studied semiconductor device shown in FIG.
30
.
A semiconductor device
70
is manufactured using a rectangular substrate
71
. The substrate
71
is formed of a metal (e.g., CuMo plate) which is superior in thermal conductivity so that heat generated from a semiconductor chip is transferred promptly to an installed radiation board or mounting substrate, thus serving also as a heat sink.
A quadrangular frame
72
is fixed by bonding (silver soldering) centrally onto the substrate, or heat sink,
71
, the frame
72
having a width smaller than the width of the heat sink
71
and having a length shorter than long sides of the heat sink
71
. The heat sink
71
serves as a source electrode. Screwing grooves
73
are formed centrally of both ends of the heat sink
71
at positions spaced apart from the frame
72
.
As shown in
FIG. 31
, the frame
72
comprises a frame-shaped ceramic base
74
and two frame-shaped ceramic sleeves
75
superimposed successively on the ceramic base
74
. A metallized surface layer
75
a
(the dotted region in
FIGS. 28 and 30
) is formed on the surface of the upper ceramic sleeve
75
.
Along the width of the heat sink
71
the ceramic sleeves
75
are superimposed one on the other at the same width as the width of the ceramic base
74
so that their inner and outer wall surfaces are in registration with the ceramic base, while in the long sides of the heat sink
71
the ceramic sleeves
75
are smaller in width than the ceramic base
74
and the surface of the ceramic base is exposed to both inside and outside of the ceramic sleeves
75
.
On the surface of the ceramic base
74
extending along the long sides of the heat sink
71
there is formed an electrically conductive metallized layer
76
. Consequently, the metallized layer
76
is exposed to the surface portions of the ceramic base
74
inside and outside the ceramic sleeves
75
. The metallized layer portions located inside the ceramic sleeves
75
serve as bonding posts
76
a
for wire connection, while the metallized layer portions located outside the ceramic sleeves
75
serve as lead connecting portions
76
b
for lead connection.
An inner end of a drain lead
77
formed of a broad metallic plate is fixed to the lead connecting portion
76
b
extending along one long side of the heat sink
71
, and an inner end of a gate lead
78
formed of a broad metallic plate is fixed to the lead connecting portion
76
b
extending along the other long side of the heat sink
71
. One corner of the drain lead
77
is cut off obliquely, serving as an electrode index
77
a
for recognition of a drain electrode (see FIG.
28
). The metallic plates which constitute the drain lead
77
and the gate lead
78
are formed of Kovar or Fe—Ni alloy, having such characteristics as thermal expansion coefficient and thermal expansion coefficient difference of ceramic being small and has a resistance to a high temperature in silver soldering.
On an upper surface of the heat sink
71
located inside the frame
72
there are fixed a capacitor chip
79
, an SiMOSFET chip
80
, and a capacitor chip
81
side by side from the drain lead
77
toward the gate lead
78
. In the capacitor chips
79
and
81
, an oxide film (SiO
2
film) is formed on a silicon substrate and an electrode is formed thereon to afford a predetermined capacitance. The silicon substrate serves as one electrode, while the electrode on the oxide film serves as the other electrode. These chips are fixed by AuSi eutectic, which is satisfactory in heat radiating property and electric conductivity and high in reliability, to the heat sink
71
formed of a metallic plate, so that there is ensured an electric contact between the substrate-side electrode of each chip and the heat sink
71
and there is obtained a satisfactory heat radiating property.
As shown in
FIG. 30
, one end of each conductive wire
82
is connected to a drain electrode
80
d
on the SiMOSFET chip
80
, while an opposite end thereof is connected to an upper electrode
79
a
of the capacitor chip
79
at a position close to the drain lead
77
. Likewise, one end of each conductive wire
83
is connected to the upper electrode
79
a
of the capacitor chip
79
, while an opposite end thereof is connected to the bonding post
76
a
which is connected electrically to the drain lead
77
. Further, one end of each conductive wire
84
is connected to one end of a gate electrode
80
g
on the SiMOSFET
80
, while an opposite end thereof is connected to an upper electrode
81
a
of the capacitor chip
81
located close to the gate lead
78
. One end of each conductive wire
85
is connected to the upper electrode
81
a of the capacitor chip
81
, while an opposite end thereof is connected to the bonding post
76
a
which is electrically connected to the gate lead
78
.
The wires
81
to
85
are formed of aluminum wires. As to the wires connected to drain and gate electrodes, there is adopted a structure wherein plural wires are connected in parallel to ensure current capacity and high frequency characteristic (see FIG.
30
).
As shown in
FIG. 28
, a cap
87
is fixed to the frame
72
. The cap
87
is formed of a ceramic plate. As shown in
FIG. 29
, in a peripheral portion on a back side of the cap
87
, a plating film
87
a
is formed of AuSn in a frame shape correspondingly to the ceramic sleeves
75
, and the ceramic sleeves
75
are fixed through the plating film
87
a
. That is, the cap
87
is fixed to the frame
72
hermetically (hermetic seal structure) through AuSn alloy.
Along a side face of the frame
72
there is formed a side metallized layer
76
d
, as indicated with dots in FIG.
29
. The side metallized layer
76
d
provides an electric connection between the heat sink
71
serving as a source electrode and the surface metallized layer
75
a
, placing the surface metallized layer
75
a
at an equal potential to the source electrode.
Exposed portions of the heat sink
71
, drain lead
77
, gate lead
78
, surface metallized layer
75
a
, side metallized layer
7
d
, and metallized layer
76
are wholly plated with Au.
It is difficult to reduce the manufacturing cost of such a semiconductor device. More particularly, (1) a heat sink made of CuMo is closely similar in thermal expan
Hitachi , Ltd.
Miles & Stockbridge P.C.
Zarneka David A.
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