Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Metallic housing or support
Reexamination Certificate
2011-08-16
2011-08-16
Smith, Zandra V. (Department: 2822)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Metallic housing or support
C438S106000, C438S108000, C438S127000, C257S737000, C257S774000, C257SE23011, C257SE23020, C257SE23068
Reexamination Certificate
active
07998796
ABSTRACT:
The present invention provides a technique capable of suppressing variations in the height of each solder ball where an NSMD is used as a structure for each land. Vias that extend through a wiring board are provided. Lands are formed at the back surface of the wiring board so as to be coupled directly to the vias respectively. The lands are respectively formed so as to be internally included in openings defined in a solder resist. Half balls are mounted over the lands respectively. Namely, the present invention has a feature in that the configuration of coupling between each of the lands and its corresponding via both formed at the back surface of the wiring board is taken as a land on via structure and a configuration form of each land is taken as an NSMD.
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patent: 2006-190928 (2006-07-01), None
Duong Khanh B
Mattingly & Malur, PC
Renesas Electronics Corporation
Smith Zandra V.
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