Active solid-state devices (e.g. – transistors – solid-state diode – Regenerative type switching device – Combined with field effect transistor
Reexamination Certificate
1998-12-30
2001-07-24
Meier, Stephen D. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Regenerative type switching device
Combined with field effect transistor
C257S138000, C257S139000, C257S135000
Reexamination Certificate
active
06265735
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a vertical power semiconductor device having self turn-off function and to a manufacturing method thereof.
2. Description of the Background Art
First, a conventional semiconductor device will be described.
FIG. 96
is a cross sectional view schematically showing a structure of a semiconductor device in accordance with a first prior art example. Referring to
FIG. 96
, the first prior art example has an SITh (Static Induction Thyristor). The SITh includes a pin diode porion, a p type gate region
307
, a gate electrode layer
309
, a cathode electrode
311
and an anode electrode
313
.
A pin diode portion has a stacked structure including a p
+
, anode region
301
, an n
−
region
303
and a cathode region (n
+
emitter region)
305
. The p type gate region
307
is formed in n
−
region
303
. Gate electrode
309
is electrically connected to p type gate region
307
. Cathode electrode
311
is electrically connected to cathode region
305
, and anode electrode
313
is electrically connected to p
+
anode region
301
, respectively.
The SITh can realize on-state by setting gate voltage applied to gate electrode
309
positive. At this time, current flows through pin diode from p
+
anode region
301
to the side of cathode region
305
.
FIG. 97
is a cross sectional view schematically showing a structure of a semiconductor device in accordance with a second prior art example. Referring to
FIG. 97
, the second prior art example shows a GTO (Gate Turn-Off) thyristor. The GTO thyristor has a p
+
anode region
351
, an n
−
region
353
, a p base region
355
, a cathode region
357
, a gate electrode
359
, a cathode electrode
361
and an anode electrode
363
.
The p
+
anode region
351
, n
−
region
353
, p base region
355
and cathode region
357
are stacked successively. The p type base region
355
is electrically connected to gate electrode
359
. Cathode electrode
361
is electrically connected to cathode region
357
, and anode electrode
363
is electrically connected to p
+
anode region
351
, respectively.
In this GTO thyristor also, on-state can be realized by setting the gate voltage positive. By setting gate voltage positive, current flows through a pnpn diode from p
+
corrector region
351
to the side of cathode region
357
.
Both in the first and second prior art examples, off-state can be realized by applying a negative voltage to the gate electrode. When a negative voltage is applied to gate electrode
309
or
359
, minority carriers (holes) remaining in the device are extracted from gate electrode
309
or
359
. Thus, the main current is cut off.
FIG. 98
is a cross sectional view schematically showing a structure of a semiconductor device in accordance with a third prior art example. Referring to
FIG. 98
, the third prior art example shows an example of a trench IGBT (Insulated Gate Bipolar Transistor). The trench IGBT includes a p
+
collector region
101
, n
+
buffer region
103
, n
−
region
105
, p type base region
107
, n
+
emitter region
109
, a p
+
contact region
111
, a gate oxide film
115
, a gate electrode layer
117
, a cathode electrode (emitter)
121
and an anode electrode (collector)
123
. On p
+
collector region
101
, n
−
region
105
is formed with n
+
buffer region
103
interposed. On n
−
region
105
, n
+
emitter region
109
and p
+
contact region
111
are formed adjacent to each other with p type base region
107
interposed. On the surface where n
+
emitter region
109
is formed, there is provided a trench
413
.
Trench
413
passes through n
+
emitter region
109
and p type base region
107
and reaches n
−
region
105
. The depth T
P
of trench
413
from the surface is 3 to 5 &mgr;m.
Along inner wall surface of trench
413
, gate oxide film
115
is formed. Gate electrode layer
117
is formed to fill the trench
413
and with its upper end projecting from trench
413
. Gate electrode layer
117
opposes to n
+
emitter region
109
, p type base region
107
and n
−
region
105
with gate oxide film
115
interposed.
Interlayer insulating layer
119
is formed to cover an upper end of gate electrode layer
117
. In interlayer insulating layer, there is provided an opening which disposes the surfaces of n
+
emitter region
109
and p
+
contact region
111
. Cathode electrode (emitter)
121
is formed so as to electrically connect n
+
emitter region
109
and p
+
contact region
111
through the opening. Anode electrode (collector)
123
is formed to be electrically connected to p
+
collector region
101
.
Hereinafter, the surface of the semiconductor substrate on which cathode electrode
121
is formed will be referred to as a cathode surface or a first main surface, and the surface where anode electrode
123
is formed will be referred to as an anode surface or the second main surface.
A trench MOS gate structure in which gate electrode layer
117
is formed in trench
413
with gate oxide film
115
interposed is manufactured through the following steps.
First, in a semiconductor substrate, a relatively deep trench
413
of about 3 to about 5 &mgr;m is formed by common anisotropic dry etching. Sacrificial oxidation or cleaning is performed on the inner wall of trench
413
. Thereafter, a silicon thermal oxide film (hereinafter referred to as a gate oxide film)
115
is formed at a temperature from 900° C. to 1000° C. in, for example, vapor ambient (H
2
O). A polysilicon film doped with an n type impurity such as phosphorous or a polycrystalline silicon film doped with a p type impurity such as boron fills the trench
413
. The doped polysilicon film is patterned so that trench
413
is filled and doped polysilicon film is drawn out at least from a porion of trench
413
to the surface of the cathode side. The patterned doped polysilicon film is electrically connected to a gate surface interconnection formed of a metal such as aluminum, provided entirely over the semiconductor device, while insulated from cathode electrode
121
.
The method of controlling on-state and off-state in the third prior art example will be described.
On-state is realized by applying a positive (+) voltage to gate electrode
117
while a forward bias is applied between cathode electrode
121
-anode electrode
123
, that is, while a positive (+) voltage is applied to anode electrode
123
and a negative (−) voltage is applied to cathode electrode
121
.
A turn-on process in which the device transits from off-state to the on-state will be described in the following.
When a positive (+) voltage is applied to gate electrode layer
117
, an n channel (inverted n region) which is inverted to n type and having very high electron density is generated at p base region
107
near gate oxide film
115
. Electrons, which are one of the current carriers (hereinafter referred to as carriers) are injected from n
+
emitter region
109
through the n channel to n
−
region
105
, and flow to p
+
collector region
101
to which the positive (+) voltage is applied. When the electrons reach p
+
collector region
101
, holes, which are other current carrier are injected from p
+
collector region
101
to n
−
region
105
and flow to n
+
emitter region
109
to which the negative (−) voltage is applied. Thus, the flow reaches the position where the aforementioned n channel is in contact with n
−
region
105
. This process is referred to as storage process, and the time necessary for this process is referred to as storage time (t
storage
) or turn-off delay time (td(
off
)). Power loss during the storage time is so small that it can be neglected, as compared with steady loss, which will be described layer.
Thereafter, from anode electrode
123
and cathode electrode
121
, sufficient current carriers a
Harada Masana
Minato Tadaharu
Nakamura Katsumi
Takahashi Tetsuo
McDermott & Will & Emery
Meier Stephen D.
Mitsubishi Denki & Kabushiki Kaisha
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