Semiconductor device and manufacturing method thereof

Details Semiconductor device and manufacturing method thereof Semiconductor device and manufacturing method thereof

1987-10-22

1989-04-04

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 27, 437 28, 437 41, 437 45, 437 48, 437 51, 437 52, 437193, H01L 21265, B01J 1700

Patent

active

048187160

ABSTRACT:
Disclosed are memory cells of a vertical-type read only memory (ROM) having a plurality of MISFETs connected in series. The MISFETs include gate electrodes formed with multiple conductive layers, in which some of the MISFETs are set to the depletion type and at least some of the remaining MISFETs are set to the enhancement type, so as to write information in the memory cells. The information write operation is conducted through at least two steps. Namely, in the first information write step, gate electrodes are used as a mask to implant an impurity; and in the second step, an impurity is implanted through the gate electrodes into the surface of the semiconductor substrate. These steps enable a semiconductor memory device, such as a vertical-type mask ROM having memory cells with a reduced series resistance and being suitable for a high degree of integration, to be produced.
Furthermore, there is disclosed a memory structure of a semiconductor memory device suitable for a higher degree of integration through an arrangement of gate electrodes of multiple layers.

REFERENCES:
patent: 4295209 (1981-10-01), Donley
patent: 4342100 (1982-07-01), Kuo
patent: 4356042 (1982-10-01), Gedaly et al.
patent: 4358889 (1982-11-01), Dickman et al.
patent: 4364167 (1982-12-01), Donley
patent: 4500975 (1985-02-01), Shirato

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