Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Metallic housing or support
Reexamination Certificate
2001-03-23
2004-02-10
Graybill, David E. (Department: 2827)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Metallic housing or support
C438S123000, C438S124000
Reexamination Certificate
active
06689642
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a semiconductor device and a manufacturing method thereof, especially to a semiconductor device having large electrodes on primary planes for letting large currents pass through, such as source and drain electrode of the power MOSFET, which will be termed as current passage electrodes hereinafter, and a manufacturing method for assembling the same semiconductor device.
BACKGROUND OF THE INVENTION
Recently, with the growth of the mobile computing/communication terminal market there has been an increasing demand for small and yet larger capacity lithium-ion batteries. The protecting circuit board for the management of charging and discharging the lithium-ion battery has to be small in order to meet the need for total weight reduction of the mobile computing/communication terminal and to withstand short circuits due to excessive loads. In this application, it was required that the protecting circuit board be small, as the board was housed inside the container of the lithium-ion battery. This size reduction has been accomplished by use of COB (Chip on Board) technology using multiple chip components. On the other hand, as the switching devices are connected to the lithium-ion battery in series, there was also a need for reducing the on-state resistance of the switching devices. This is an indispensable ingredient in mobile telephone applications for extending the calling period and the stand-by period.
For achieving a low on-state resistance (R
DS(on)
), developments have been made for increasing the cell density by applying micro-fabrication technology to the chip manufacturing process. As a result, in a planar structure where the channels were formed on the surface of the semiconductor substrates, the cell density was 7.4 million per square inch and the on-state resistance was 27 m&OHgr;. Further, in the first-generation trench structure where the channels were formed along the side of the trench, the cell density was 25 million per square inch and the on-state resistance was reduced to 17 m&OHgr;. Improvements were made in the second-generation trench structure so that the cell density reached 72 million per square inch and the on-state resistance decreased to 12 m&OHgr;. However, as there are limitations to this micro-fabrication technology, it is not likely that the on-state resistance can be to be significantly reduced further based on the same approach.
FIG. 11
is a cross-sectional view of a power MOSFET mounted on the conventional protecting circuit board described above. MOSFET bare chip
23
is fixed on a header
21
of a frame punched out from a copper material through a pre-form
22
made of a solder or a silver paste. A gold electrode (not shown in the figure) is formed as a drain electrode by sputtering on the bottom face of the power MOSFET bare chip
23
, and a gate electrode and a source electrode are formed on the top face by evaporating aluminum. As shown as well in
FIGS. 12 and 13
, the drain terminals
25
of the frame and the header
21
are joined for making direct connection with the drain electrode. The gate terminal
26
and source terminal
27
are electrically connected to the gate electrode and source electrode, respectively, by ball bonding using a gold bonding wire
24
. Thus, for reducing the on-state resistance of the power MOSFET, the electric resistances of the materials forming the frame, the pre-form, bonding wire
24
and the source electrode on the top face of the chip have to be taken into account.
FIG.
12
and
FIG. 13
are plan views that depict conventional designs of the bonding wires used for reducing the on-state resistance.
The design shown in
FIG. 12
is supposed to improve the electric current capacity by increasing to four the number of the bonding wires
24
which connect the source electrode and the source terminal
27
. The design shown in
FIG. 13
with two short and two long bonding wires connecting the source electrode and the source terminal
27
is supposed to improve the electric current capacity and, at the same time, to reduce the electrical resistance of the source electrode by expanding the region for the bonding.
FIG. 9
is a table that compares the on-state resistance depending on the assembling structure of the conventional power MOSFET with this invention. Both samples A and B are of a conventional SOP8 type mold structure, with sample A having the structure shown in FIG.
12
and sample B having the structure shown in FIG.
13
. It is seen that changing the bonding wire configuration from a four short wire combination to a two short and two long wire combination reduced the on-state resistance from 13.43 m&OHgr; to 12.10 m&OHgr;, by 1.33 m&OHgr;.
SUMMARY OF THE INVENTION
According to this invention, it is possible to achieve an on-state resistance low enough to meet the above demand by drastically altering the conventional assembling structure of the semiconductor devices including power MOSFET and by changing the manufacturing method thereof. This invention provides a means for the connection with the source electrode which serves as the most dominant current passage electrode on the top face of the semiconductor chip, in contrast to the conventional means where the connection is made through wire bonding and only one frame is used for other connections. This is realized by fixing an electrode integral with a lead on the electrodes including the current passage electrode, which will hereinafter be termed a “connection electrode.”
Thus, the semiconductor device of this invention includes:
a lower frame having a header for fixing a semiconductor chip thereon and having external leads combined with the header as one unit;
a semiconductor chip fixed on the header;
an upper frame having a connection electrode fixed on a current passage electrode formed on the top face of the semiconductor chip and having external leads combined with the connection electrode as one unit; and
a resin mold covering the header and a portion of the external leads of the lower frame, and covering the connection electrode and a portion of the external leads of the upper frame.
In this configuration, the semiconductor chip can be die-bonded onto the header, and the connection electrode can be large enough to cover most of the current passage electrode of the semiconductor chip when the connection electrode is fixed on the current passage electrode. This makes it possible to reduce the on-state resistance by as much as 30% in comparison with the conventional configuration where wire bonding is used for the connection between the current passage electrode and the corresponding leads.
Furthermore, this configuration provides a structure with extremely high heat dissipation, as the bottom face of the semiconductor chip is fixed on the header of the lower frame and the most of the top face of the semiconductor chip is connected to the connection electrode. Unlike the conventional connection using a gold bonding wire, the connection electrode can avoid melting and dissipate heat rapidly in the event of excessive current flow or short circuit due to excessive charge. Thus, this configuration provides an assembling structure for semiconductor devices with extremely high durability.
Still furthermore, as this configuration provides low enough on-state resistance as well as high enough heat dissipation, it is possible to make the size of the semiconductor chip even smaller, provided that the target specifications remain the same as the conventional ones. Thus, this invention makes it possible to meet the increasing demand for size reduction of the protecting circuit boards.
The method of manufacturing the semiconductor device of this invention includes:
preparing a lower frame having a header for fixing a semiconductor chip thereon and having external leads combined with the header as one unit;
fixing a semiconductor chip on the header;
preparing an upper frame having a connection electrode fixed on an electrode formed on the top face of the semiconductor chip and having external leads combin
Graybill David E.
Morrison & Foerster / LLP
Sanyo Electric Co,. Ltd.
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