Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Assembly of plural semiconductive substrates each possessing...
Reexamination Certificate
2003-07-18
2004-11-09
Zarneke, David (Department: 2829)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Assembly of plural semiconductive substrates each possessing...
C438S109000, C438S113000, C438S127000, C438S458000
Reexamination Certificate
active
06815255
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to semiconductor devices having multiple semiconductor chips layered on one another and manufacturing methods thereof. The invention more particularly relates to a semiconductor device including two semiconductor chips having their circuit forming surfaces opposed to one another, and electrodes formed on the circuit forming surfaces being electrically connected with one another, and a manufacturing method thereof.
In recent years, with the advent of smaller size electronic devices capable of high speed processing, a three-dimensional structure including two or more kinds of semiconductor chips layered on one another has come to be widely researched and developed.
Such a conventional three-dimensional semiconductor device will be now described.
FIG. 18
is a sectional view of the conventional semiconductor device.
As shown in
FIG. 18
, the conventional semiconductor device includes a first semiconductor chip
1
and a second semiconductor chip
4
. The first semiconductor chip
1
has first electrodes
2
and bonding pads
3
on a first main surface. The second semiconductor chip
4
is provided with second electrodes
5
on a second main surface and has a smaller area than the first semiconductor chip
1
. Herein, the first and second semiconductor chips
1
and
4
are integrated so that their main surfaces (i.e., the circuit forming surfaces) are opposed to one another and the first and second electrodes
2
and
5
are electrically connected with one another. Stated differently, while the first and second electrodes
2
and
5
are registered, the second semiconductor chip
4
is placed facedown on the first semiconductor chip
1
. More specifically, the first and second electrodes
2
and
5
are connected through a metal bump
7
, while the part of the second electrode
5
in contact with the metal bump
7
is provided with a barrier metal layer
6
. The bonding pads
3
are provided outside the region of the first main surface of the first semiconductor chip
1
opposed to the second main surface of the second semiconductor chip
4
. There is a resin layer
8
filled between the first main surface of the first semiconductor chip
1
and the second main surface of the second semiconductor chip
4
. More specifically, the first and second semiconductor chips
1
and
4
are adhered by the resin layer
8
into an integrated form.
The surface of the first semiconductor chip
1
opposite to the first main surface is secured to a die pad portion
9
a
by conductive paste
10
containing palladium (Pd), silver (Ag) or the like. The bonding pad
3
, and a lead portion
9
b
provided adjacent to the die pad portion
9
a
are electrically connected with one another through a thin metal bonding wire
11
. Note that the die pad portion
9
a
and the lead portion
9
b
are cut from a single lead frame
9
. The first and second semiconductor chips
1
and
4
, the die pad portion
9
a
, the lead portions
9
b
and the bonding wires
11
are encapsulated in a resin package
12
.
A method of manufacturing the conventional semiconductor device will be now described.
FIGS. 19A
,
19
B,
20
A and
20
B are sectional views showing steps in the method of manufacturing the conventional semiconductor device.
As shown in
FIG. 19A
, the first and second semiconductor chips
1
and
4
are registered. More specifically, a plurality of first electrodes
2
and a plurality of bonding pads
3
are provided on a first main surface of the first semiconductor chip
1
. The chip
1
is then placed on a packaging jig (not shown) and a resin
8
A is applied on the first main surface of the semiconductor chip
1
. The second semiconductor chip
4
having a plurality of second electrodes
5
on a second main surface is prepared over the first semiconductor chip
1
so that their main surfaces, i.e., their circuit forming surfaces are opposed to one another. Then, after a plurality of metal bumps
7
are formed on the second electrodes
5
, the first and second electrodes
2
and
5
are registered. Note that there is a barrier metal layer
6
provided on the part of the second electrodes
5
in contact with the metal bumps
7
.
Then, as shown in
FIG. 19B
, the first and second semiconductor chips
1
and
4
are joined with one another. More specifically, the second semiconductor chip
4
is heated and pressed using a metal tool
13
from the surface opposite to the second main surface. As a result, the first electrodes
2
on the first semiconductor chip
1
and the second electrodes
5
on the second semiconductor chip
4
are joined with one another through the metal bumps
7
formed on the second electrodes
5
(more precisely on the barrier metal layers
6
) on the second semiconductor chip
4
. Then, the resin
8
A filled between the joined first and second semiconductor chips
1
and
4
is irradiated with ultraviolet rays or heated for curing and a resin layer
8
results.
Then, as shown in
FIG. 20A
, the joined first and second semiconductor chips
1
and
4
in an integrated form (hereinafter referred to as a “chip-layered body”) is subjected to wire-bonding. More specifically, a lead frame
9
having a die pad portion
9
a
and lead portions
9
b
is prepared. Then, the surface opposite to the first main surface of the first semiconductor chip
1
is secured onto the die pad portion
9
a
using conductive paste
10
containing Pd, Ag or the like. The bonding pads
3
on the first semiconductor chip
1
and the lead portions
9
b
are then electrically connected through thin metal bonding wires
11
. Thus, the electrical connection for the semiconductor device is completed.
As shown in
FIG. 20B
, the chip-layered body after the wire-bonding step is encapsulated in a resin. More specifically, the first and second semiconductor chips
1
and
4
, the die pad portion
9
a
, the lead portions
9
b
and the bonding wires
11
are encapsulated in a resin package
12
. Note however that the bottom surface of the die pad portion
9
a
and the bottom and outer side surfaces of the lead portions
9
b
(the side surfaces opposite to the side facing the die pad portion
9
a
) are exposed out of the resin package
12
. Thus, the bottom and outer side surfaces of the lead portions
9
b
serve as external terminals.
However, the conventional semiconductor device and the manufacturing method thereof described above suffer from the following disadvantages. The thickness of the semiconductor device having multiple layers of semiconductor chips increases in proportion to the number of the semiconductor chips used. For example, in the conventional semiconductor device shown in
FIG. 18
, the thickness of the first and second semiconductor chips
1
and
4
is each about in the range from 200 to 300 &mgr;m even after the back surface (the surface opposite to the circuit forming surface (main surface)) is polished. The metal bumps
7
used to join the first and second semiconductor chips
1
and
4
are about as thick as several tens &mgr;m after the joining. In addition, if the chip-layered body including the first and second semiconductor chips
1
and
4
is die-bonded to the die pad portion
9
a
as thick as several hundreds &mgr;m and the die-bonded chip-layered body as a whole is encapsulated in the resin package
12
, the completed semiconductor device has a thickness about as large as 1 mm. Such a thickness is about the same as the thickness of the thin type packages widely used in recent years, which suggests how hard it could be to reduce the size of semiconductor devices having such a chip-layered body.
Meanwhile, semiconductor chips with large thickness in a semiconductor device could impede thermal radiation from the semiconductor chips, and therefore the heat radiation property of the semiconductor device as a whole could be lowered.
SUMMARY OF THE INVENTION
In view of the foregoing, it is an object of the present invention to reduce the thickness of a chip-layered body forming a semiconductor device, and allow the semiconductor device to hav
Fujimoto Hiroaki
Kaneko Hideyuki
Matsumura Kazuhiko
Nagao Koichi
Nakaoka Yukiko
Geyer Scott B.
Nixon & Peabody LLP
Studebaker Donald R.
Zarneke David
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