Semiconductor device manufacturing: process – Bonding of plural semiconductor substrates – Thinning of semiconductor substrate
Reexamination Certificate
2003-02-26
2004-06-22
Fahmy, Wael (Department: 2814)
Semiconductor device manufacturing: process
Bonding of plural semiconductor substrates
Thinning of semiconductor substrate
C438S977000, C257S619000
Reexamination Certificate
active
06753238
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method thereof, and particularly relates to a thinned semiconductor wafer or thinned semiconductor chip and a forming method thereof.
2. Description of the Related Art
In recent years, an IC or LSI has been increasingly accelerated to have higher integration and larger capacity. To address this trend, a semiconductor chip is fabricated in a CSP (chip size package) in order to incorporate the CSP within a portable device and as the portable device becomes small and is made to have high performance, the CSP is required to occupy smaller area and have a smaller height for dense integration of CSPs. Furthermore, an MCP (multi-chip package) incorporating a plurality of semiconductor chips therein has been put into practical use.
Furthermore, as an information technology has been rapidly spread and is now in use for variety technical fields, semiconductor devices constituting an information processing device increasingly need to be fabricated as a system LSI. Additionally, a variety of functional blocks including a plurality of semiconductor chips such as compound semiconductor chips formed of an optical device/high frequency device need to be integrated as a system LSI, increasingly requiring a packaging technique for electronic system integration.
In order to achieve high-density packaging of semiconductor chips, a semiconductor chip needs to be thinned, in more detail, thinned to a thickness of 50 &mgr;m or less.
A semiconductor chip typically can be thinned by grinding or etching a backside of a semiconductor wafer. Such a technique is described in, for example, JP 08-316194 A or JP 2001-223202 A. A conventional technique will be explained below with reference to
FIGS. 1A
to
1
C.
As shown in
FIG. 1A
, a protection tape
102
is bonded to a surface of a semiconductor wafer
101
. Then, the protection tape
102
bonded to the semiconductor wafer
101
is fixed in a vacuum state to a grinding suction stage
103
and the grinding suction stage
103
is made to rotate, with a rear surface of the semiconductor wafer
101
being in contact with a rotating grind stone
104
, in order to grind the rear surface thereof. Then, the semiconductor wafer
101
is thinned to a predetermined thickness of, for example, approximately 100 &mgr;m.
Thereafter, the semiconductor wafer is removed from a grinding device. As a result, as shown in
FIG. 1B
, the protection tape
102
bonded to the surface of the thinned semiconductor wafer
101
a
is obtained. In this case, the protection tape
102
causes the thinned semiconductor wafer
101
a
to slightly be bended.
The protection film
102
is peeled from the thinned semiconductor wafer
101
a
and the semiconductor wafer
101
a
is diced into semiconductor chips
105
. That is, as shown in
FIG. 1C
, an expansion sheet
106
is bonded to the rear surface of the semiconductor wafer
101
a
and the wafer
101
a
is mounted onto a dicing device, and then, the semiconductor wafer
101
a
is diced from the front surface thereof. Thereafter, the expansion sheet
106
is elongated to produce the individual semiconductor chips
105
.
As described above, in the high-density packaging of semiconductor devices, particularly in the CSP, a semiconductor chip has to be thinned. For example, the semiconductor chip needs to be of a thickness of 50 &mgr;m or less.
However, the thinned semiconductor wafer formed using the prior art explained in the description of
FIGS. 10A
to
10
C is increasingly bended when being thinned, leading to a significant reduction in the yield of a semiconductor device. This is because the thinned semiconductor wafer cannot be mounted in place on the stage and the extremely bended chip is easily destroyed in the step of dicing a wafer.
Furthermore, when making a semiconductor wafer have a film thickness of approximately 20 &mgr;m, a wet etching has to additionally be performed after grinding the rear surface of the wafer. In this case, when the wafer is bended, the wafer is etched to have large variations in its thickness. Therefore, a large number of semiconductor chips having a thickness beyond an allowable range of thickness are produced, lowering the yield of a semiconductor device.
The problem found in the above-described conventional technique for thinning a semiconductor wafer becomes enlarged as a diameter of the semiconductor wafer increases (for example, a semiconductor wafer of a diameter of 12 inches).
SUMMARY OF THE INVENTION
The present invention has been made in view of the above, and therefore has a main object to provide a semiconductor device that facilitates reduction in film thickness of a semiconductor chip and a manufacturing method thereof. Further, another object of the present invention is to simplify a technique of high-density mounting of semiconductor devices and facilitate application of the technique to mass production.
Therefore, according to a first aspect of the present invention, a method of manufacturing a semiconductor device includes the steps of: forming at least one electrode at a specific position on a semiconductor wafer, the specific position being located on a surface of the semiconductor wafer; bonding a reinforcing plate to a surface of the at least one electrode while interposing a first resin layer between the surface of the semiconductor wafer and the reinforcing plate via an adhesive; thinning the semiconductor wafer by removing a portion of the semiconductor wafer; and covering an exposed surface of the semiconductor wafer with a second resin layer, the exposed surface being produced by removing the portion of the semiconductor wafer.
According to a second aspect of the present invention, a method of manufacturing a semiconductor device includes the steps of: forming at least one electrode at a specific position on a semiconductor wafer having an SOI (Silicon On Insulator) structure, the specific position being located on a surface of the semiconductor wafer, the SOI structure being defined such that an insulation layer is formed over a silicon substrate and an active silicon layer is formed over the insulation layer; forming a first resin layer between the at least one electrode on the surface of the semiconductor wafer; thinning the semiconductor wafer by removing the silicon substrate of the semiconductor wafer to expose the insulation layer; and covering an exposed surface of the insulation layer with a second resin layer.
According to a third aspect of the present invention, a semiconductor device includes: at least one electrode formed at a specific position on a semiconductor wafer, the specific position being located on a surface of the semiconductor wafer; a first resin layer interposed between the at least one electrode formed at a specific position on a semiconductor wafer and formed on the surface of the semiconductor wafer; and a second resin layer formed on an opposite surface of the semiconductor wafer, the opposite surface being produced by removing a portion of the semiconductor wafer, the portion being located opposite the surface of the semiconductor wafer.
According to the present invention, the semiconductor wafer rarely bends after the wafer is thinned and variation in thickness of the thinned semiconductor wafer is significantly reduced. Therefore, the wafer can be handled without breaking or damaging the wafer in the step of thinning a semiconductor wafer, thereby improving the yield of semiconductor wafer.
Moreover, according to the present invention, dense packaging of semiconductor chips is extremely facilitated. Then, when implementing the CSP technique according to the present invention, the semiconductor chip can extremely be thinned in a simplified manner. Therefore, cracks that are caused in a solder ball connection portion and due to a difference between thermal expansion coefficients of the connection portion and a motherboard to which the CSP is mounted can significantly be reduced, which cracks are developed when implement
Fahmy Wael
Hayes & Soloway P.C.
NEC Electronics Corporation
Pham Hoai
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