Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
2002-01-09
2004-01-27
Coleman, W. David (Department: 2823)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S405000, C438S424000, C438S692000
Reexamination Certificate
active
06682985
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method thereof, in particular, to a semiconductor device, which has a trench separation band, and a manufacturing method thereof.
2. Description of the Background Art
Insulating separation bands are provided in many places of a semiconductor substrate in a semiconductor device such as a DRAM (dynamic random access memory), an SRAM (static random access memory) and a flash memory. Though LOCOS (local oxidation of silicon) separation has been in conventional use, as the miniaturization of the above described semiconductor devices has progressed, trench separation bands suitable for miniaturization have come to be exclusively used for separation bands.
Next, a process for a general trench separation band is described in reference to the figures. First, a base silicon oxide layer (SiO
2
film)
102
, whose thickness is, for example, 50 nm, is formed on a silicon substrate
101
. Base silicon oxide layer
102
is formed for the purpose of height adjustment of the trench separation band. Then, a polycrystalline silicon layer
103
, whose thickness is 100 nm, is deposited on the base silicon oxide layer. In addition, a silicon nitride layer (SiN film)
104
, whose thickness is 300 nm, is deposited thereon (FIG.
15
). Silicon nitride layer
104
functions as a stopper layer during CMP polishing.
After this, a photoresist pattern
105
is formed which corresponds to regions where the trench separation bands are desired to be provided. Then, silicon nitride layer
104
is patterned by using this photoresist pattern as a mask (FIG.
16
). After this, photoresist pattern
105
is removed. Then, polycrystalline silicon layer
103
and silicon oxide layer
102
are etched by using patterned silicon nitride layer
104
as a mask. Furthermore, a trench
106
, whose depth is, for example, 0.5 &mgr;m, is created in the silicon substrate by using these patterns as a mask (FIG.
17
). Polycrystalline silicon layer
103
makes it easy for an inner wall silicon oxide film to be formed. In addition to this, polycrystalline silicon layer
103
protects the silicon substrate at the time when the silicon oxide film filled into the trench separation band is etched.
After this, the damaged layer on the trench surface is removed and, after that, a silicon oxide film (hereinafter referred to as inner wall oxide film)
107
is formed in the inner wall of the trench with a thickness of, for example, 120 nm (FIG.
18
). This inner wall oxide film
107
functions as a short circuit prevention insulating film of silicon substrate
101
as described below. In addition, at the same time, it functions as a layer that relieves stress due to the difference in the thermal expansion coefficients of the filled-in silicon oxide film (hereinafter referred to as filled-in oxide film), which is filled into the trench, and silicon substrate
101
.
Next, the above described filled-in insulating layer
108
is deposited with a thickness of 1 &mgr;m so as to fill in trench
106
, on which inner wall oxide film
107
has been formed (FIG.
19
). After this, CMP polishing is carried out by utilizing slurry, whose main component is silicon oxide (SiO
2
). As for CMP polishing, the polishing rates within the wafer surface area are taken into consideration and polishing is carried out until, at least, silicon nitride layer
104
is exposed (FIG.
20
).
At the time of this CMP polishing the unevenness of the polishing rates is taken into consideration and over-etching is carried out to the degree of 10% of the thickness of an HDP (High Density Plasma) film. As a result of this over-etching, in some regions 100 nm of silicon nitride layer
104
is polished off. After this, etching is carried out by using an HF liquid so as to make filled-in oxide film
108
lower by 250 nm for the purpose of adjustment of the height of the trench separation (FIG.
21
). Next, the silicon nitride layer, the polycrystalline silicon layer and the base silicon oxide layer are removed. As a result of this, as shown in
FIG. 22
, a trench separation band, whose height from the silicon substrate surface is approximately 50 nm, that is, in the range of 0 nm to 100 nm, can be formed.
A trench separation band which has a conventional width can be formed by using the above described method. In the formation of the trench separation band with a conventional width, as shown in
FIG. 20
, the top surface of the trench oxide film and the top surface of the silicon nitride layer become a shared surface.
When a trench silicon oxide layer (hereinafter referred to as trench oxide layer or trench oxide film) is filled into a wide trench in order to form a wide trench separation band by means of the above described method, however, trench oxide layer
108
in a form as shown in
FIG. 23
is formed. After this, the trench oxide layer is polished through CMP polishing and silicon nitride layer
104
is exposed. At this time, the top surface of trench silicon oxide film (hereinafter referred to as trench oxide film or trench oxide layer)
108
of the wide trench becomes lower than the top surface of silicon nitride layer
104
so as to form a recess in a dish form (FIG.
24
). This trench oxide film is, in some cases, referred to as a filled-in oxide film in the description hereinafter. Concretely, the top surface of filled-in oxide film
108
of the wide trench is, for example, 100 nm lower than the top surface of silicon nitride layer
104
.
After this, etching is carried out by using an HF liquid so as to reduce the thickness of the filled-in oxide film by, for example, 250 nm for the purpose of adjustment of the height of the trench separation band. In some cases as a result of this etching by using the HF liquid, as shown in
FIG. 25
, silicon substrate
101
is exposed beneath an edge portion of base silicon oxide layer
102
in the upper portion of a sidewall of the wide trench. After this, when polycrystalline silicon layer
103
is removed through etching, the exposed portion of the silicon substrate, which is also made of silicon, is etched. As a result of this, the exposed portion of silicon is scooped out in an inward direction and, as shown in
FIG. 26
, a cavity
111
is created.
In the case that such a scooping out occurs, the wide trench separation band cannot sufficiently function so as to isolate, without fail, respective regions in the silicon substrate by means of an insulating layer. Therefore, a short circuit, or the like, occurs.
A phenomenon wherein a silicon substrate is scooped out due to etching of a filled-in oxide film in a trench separation band, as described above, is known conventionally and several methods for preventing the silicon substrate from being scooped out have been proposed. For example, a method has been proposed wherein the filled-in oxide film is etched after being flattened through polishing so that the difference in the levels of the oxide film in the active region on which semiconductor elements are to be formed (Japanese Patent Laying-Open No. 2000-68365). In this method, however, the creation of a recess in a dish form is not supposed to occur through CMP polishing of the filled-in insulating layer of the wide trench separation band. Therefore, it cannot be used for the formation of the wide trench separation band which is the subject of the present invention.
In addition, a method has been proposed wherein a thermal oxide film, which has strong withstanding properties against etching, is formed not only on the inner walls of the trench but, also, on the side surfaces of the filled-in oxide film which protrudes above the silicon substrate surface (Japanese Patent Laying-Open No. 10-340950). However, this method is not effective in the case that a recess in a dish form occurs through CMP polishing in the filled-in insulating layer of the wide trench separation band.
In addition, in the case that intervals of active regions
130
wherein semiconductor elements are formed become wide, a structure
Tsuji Naoki
Yuzuriha Kojiro
Coleman W. David
Maldonado Julio J.
McDermott & Will & Emery
Renesas Technology Corp.
LandOfFree
Semiconductor device and manufacturing method thereof does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor device and manufacturing method thereof, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device and manufacturing method thereof will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3245625