Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With contact or lead
Reexamination Certificate
2001-03-13
2004-01-06
Wong, Don (Department: 2823)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
With contact or lead
C257S701000, C257S758000
Reexamination Certificate
active
06674162
ABSTRACT:
TECHNICAL FIELD
This invention relates to a semiconductor device and a manufacturing method thereof and, in particular, to a technology for improving the reliability of chip size package. The chip size package, also called CSP, includes the package of the same size as a chip as well as the package of a size slightly larger than a chip, and is used for achieving highly concentrated mounting. The present invention relates to the technology for improving the reliability of such chip size package.
BACKGROUND ART
In the filed described above, two structures have been used; namely, ball grid array (BGA) in which solder balls are aligned in a plane and fine-pitch BGA in which the ball pitch of the BGA is further reduced for making the package size closer to the chip size.
Also, the wafer CSP, which was described on pages 44-71 of the August issue of ‘The Nikkei Micro Device’, 1998, has attracted a lot of attentions. The wafer CSP is basically a CSP in which wires and arrayed pads are formed during the wafer process (the upstream process) before the dicing of chips. Through this method, the wafer process and the packaging process (the downstream process) can be combined into one process. Thus, it is expected to decrease the packaging cost through this technology.
There are two types of chip size package, the resin sealing type and the rewiring type. As the same as the conventional package, the resin sealing type has a configuration in which the surface of the substrate is covered with sealing resin. In particular, metal posts are formed directly on the wiring layer of the chip surface, and both the metal posts and the wiring layer are buried in the sealing resin. When the package is mounted on a print board, the stresses generated by the difference in the thermal expansion between the print board and the package are concentrated on the metal posts. It is known that the longer the metal post is, the more the generated stresses are dissipated.
On the other hand, as shown in
FIG. 13
, the rewiring type has a configuration in which rewiring is formed without the use of resin sealing. In this configuration, the A
1
electrode
52
, the wiring layer
53
on which the metal post
55
having the solder ball
56
(also called solder bump) thereon is formed, and the insulating layer
54
are laminated on the surface of the chip
51
. The wiring layer
53
is used for rewiring in order to arrange the solder balls
56
in accordance with a predetermined array design on the chip.
In case of the resin sealing type, the metal post is about a few &mgr;m long and reinforced with the sealing resin, resulting in a high reliability. However, in order to form the resin sealing, it is necessary to use a metal die in the downstream process, which makes the process complicated. On the other hand, the rewiring type requires relatively simple processing. An advantage of the rewiring type is to be able to perform almost all the processes by wafer processing. However, the rewiring type needs to improve the reliability by dissipating the stresses in one way or another.
FIG. 14
is a cross-sectional view of a configuration in which the chip size package
57
is mounted on a print board
61
. The solder ball
56
is pressed against and adhered to a copper electrode
60
of the wiring on the print board
61
for electrical connection between the package and the print board. However, since there is a difference in the thermal expansion coefficient between the print board
61
and the chip size package
57
, the solder ball
56
is often ruptured when the mounted package undergoes thermo-cycle tests. Especially, it is known that large shear stresses are generated at the boundary between the solder ball
56
and the metal post
55
.
It would be desirable to improve the endurance of the chip size package against the shear stresses for improving its reliability when it is mounted on a print board.
SUMMARY OF THE INVENTION
The present invention is directed to a semiconductor device having a high endurance against shear stresses at a boundary between a solder ball for external connection and a metal post connected to semiconductor circuits, and a manufacturing method of the semiconductor device. According to the present invention, there is provided a semiconductor device having a metal electrode pad formed on a semiconductor substrate, a wiring layer connected to the metal electrode pad and laid out on a surface of the semiconductor substrate, an insulating layer covering the surface of the semiconductor substrate including the wiring layer on the surface, an opening formed in the insulating layer, a metal post formed on the wiring layer exposed in the opening, and a solder ball mounted on the top surface of the metal post. The surface area of the top surface of the metal post is made lager than the surface area of the bottom surface of the metal post.
In this configuration, since the bonding strength of the boundary between the metal post and the solder ball against shear stress is proportional to the contact area of the two, it is possible to increase the shear strength of the boundary by making the surface area of the top surface of the metal post larger and, thereby, making its contact area with the solder ball mounted thereon larger. As the bottom surface of the metal post can be made relatively small, it is also possible to make the wirings of the wiring layer thin while maintaining high shear strength, leading to further miniaturization of the wiring structure.
Furthermore, when the metal post is made thinner in the middle than at its both ends, the metal post is flexible in the lateral directions, and, thus, capable of further dissipating the stresses generated by the difference in the thermal expansion.
According to another aspect of the present invention, there is also provided a method of manufacturing a semiconductor device having the steps of forming a wiring layer on a substrate of the semiconductor device, forming a photoresist layer on the wiring layer, forming an opening in the photoresist layer by exposure and development of the layer, heating the photoresist layer for making the opening larger at its upper end, forming a metal post in the opening in the photoresist layer deformed by the heating, and mounting a solder ball on the top surface of the metal post.
During the heating of the photoresist layer, a portion of the photoresist layer around the upper end of the opening in the photoresist layer recedes from the initial position before the heating. This makes the opening lager at its upper end, and the resultant shape of the opening is reflected on the shape of the metal post which is formed in the opening of the photoresist layer. As a result, the surface area of the top surface of the metal post is made larger than the surface area of its bottom surface, leading to an increased contact area between the metal post and the solder ball mounted thereon and, thus, improved shear strength of the boundary between the two among other improvements, as described above.
Furthermore, when the photoresist is heated at about 200° C. or higher, it is possible to make the metal post thinner in the middle than at its both ends. This makes the metal post flexible in the lateral directions, and, thus, capable of dissipating the stresses accumulated in the boundary area with improved efficiency, as described above.
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Centrifugal Stretchi
Dinh Trinh Vo
Morrison & Forester LLP
Sanyo Electric Co,. Ltd.
Wong Don
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