Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – Outside periphery of package having specified shape or...
Reexamination Certificate
2002-09-12
2004-07-06
Clark, S. V. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
Outside periphery of package having specified shape or...
C257S777000, C257S786000, C438S110000
Reexamination Certificate
active
06759745
ABSTRACT:
FIELD OF THE INVENTION
The present invention pertains to a semiconductor device and its manufacturing method.
BACKGROUND OF THE INVENTION
In recent years, with the development of small highly-functional electronic information devices, various technologies have been developed in order to further miniaturize the semiconductor packages or other semiconductor devices loaded on these electronic information devices. CSP (chip size package) has such a high density that the size of the semiconductor package is equivalent to or a little larger than the chip size. Said CSP has high reliability and is easy to handle because it has such a structure that the semiconductor chip is covered with resin or other sealing material like the conventional semiconductor package.
FIG. 14
is a cross-sectional view illustrating the basic configuration of a general CSP type semiconductor package. In this semiconductor package, semiconductor chip
1400
with an integrated circuit formed on the top surface is fixed on insulating substrate
1402
via die paste
1404
. Conductive leads
1406
are formed on the top surface of insulating substrate
1402
and are connected to solder bumps
1408
via through-holes formed in insulating substrate
1402
. An electrode pad
1420
is formed on the main substrate of semiconductor chip
1400
. Said electrode pad
1420
and conductive leads
1406
are connected to each other via conductive wires
1410
by means of wire bonding. Semiconductor chip
1400
is sealed with a sealing material
1418
made from a resin.
In the step of adhering semiconductor chip
1400
on insulating substrate
1402
, a liquid die paste is provided to the surface of insulating substrate
1402
, and semiconductor chip
1400
is pressed on the die paste to be adhered to the insulating substrate. In this case, die paste
1404
spreads out around semiconductor chip
1400
to form die paste accumulation called fillet F. In general, such spread-out of the die paste reaches a range about 200-300 &mgr;m around semiconductor chip
1400
. Even when a film-like adhesive is used instead of the die paste (liquid), the film-like adhesive will be fluidized under pressure to form the same fillet. When a fillet F is present around semiconductor chip
1400
, the bonding position B of conductive wire
1410
on conductive lead
1406
must be set relatively far away from semiconductor chip
1400
to avoid fillet F. This causes trouble in further miniaturizing the semiconductor package.
The existence of the fillet also becomes a problem in the semiconductor package with a stack structure formed by laminating multiple semiconductor chips. In the semiconductor package with the stack structure, the size of each laminated semiconductor chip is reduced as the stack is piled up in order to guarantee the region used for forming the electrode pad near the outer periphery of the top surface of each semiconductor chip. In the semiconductor package with the stack structure, however, when the semiconductor chip in the upper layer is adhered to the semiconductor chip in the lower layer, the adhesive layer spreads out of the area of the chip to form a fillet. Therefore, it is necessary to estimate the spread-out amount to determine the relative plane size of the semiconductor chip to be stacked. As a result, the plane size of the semiconductor chip in the upper layer cannot be much larger than the area of the semiconductor chip in the lower layer. This significantly restricts the package design.
Consequently, the first purpose of the present invention is to further miniaturize the semiconductor package by limiting the amount of the fillet spread out around the semiconductor chip to the minimum.
The second purpose of the present invention is to maximize the plane size of the semiconductor chip in the upper layer with respect to the semiconductor chip in the lower layer to be stacked by limiting the amount of the fillet spread out around the semiconductor chip to the minimum in the semiconductor package with a stack structure.
SUMMARY OF INVENTION
The semiconductor device of the present invention comprises an insulating substrate with a conductive lead formed on the top surface, a first semiconductor chip with a smaller bottom surface than top surface, which has an electronic circuit and an electrode pad formed on the top surface, is fixed via an adhesive to the top surface side of the aforementioned insulating substrate, a conductive wire that electrically connects the aforementioned conductive lead of the aforementioned insulating substrate to the aforementioned electrode pad of the first semiconductor chip, a sealing material that is arranged on the aforementioned insulating substrate to seal the aforementioned first semiconductor chip and the conductive wire, and an electrode used for external connection and formed on the bottom surface of the aforementioned insulating substrate opposite the top surface.
In the aforementioned structure, since the bottom surface of the first semiconductor chip is smaller than the top surface, the amount of the fillet spread out when the semiconductor chip is mounted on the insulating substrate is none or minimized with respect to the outer shape of the semiconductor chip (determined by the plane size of the top surface). Consequently, the bonding positions of the conductive wires can be guaranteed easily, and the semiconductor device can be further miniaturized.
The semiconductor device may also have a second semiconductor chip which has an electronic circuit and an electrode pad formed on the top surface and is directly fixed via an adhesive to the aforementioned top surface side of the aforementioned insulating substrate. The aforementioned second semiconductor chip can be directly fixed on the top surface of the first semiconductor chip via an adhesive.
In the semiconductor device with this structure, that is, the so-called stack structure, the plane size of the upper semiconductor chip with respect to the lower semiconductor chip to be stacked can be maximized by forming the upper semiconductor chip in such a way that its bottom surface is smaller than its top surface.
In this case, the bottom surface of the aforementioned second semiconductor chip is preferably smaller than its top surface.
In each of the aforementioned semiconductor devices, it is preferred that the edges of the aforementioned bottom surface of the aforementioned first semiconductor chip and/or second semiconductor chip form an outer peripheral end surface that slopes at a prescribed angle inwardly from each edge of the aforementioned top surface of the semiconductor chip, and the distance of the slope is in the range of 100-300 &mgr;m.
The inclination angle of the aforementioned outer peripheral end surface of the first and/or second semiconductor chip with respect to the aforementioned top surface is preferred to be in the range of 30-60°.
The semiconductor device of the present invention may also adopt such a structure that the outer peripheral end surface of the first and/or second semiconductor chip has a stepped shape instead of the aforementioned inclination.
The present invention also provides a semiconductor device manufacturing method. The semiconductor device manufacturing method provided by the present invention has the following steps: a step in which an electronic circuit and an electrode pad are formed on the top surface of a wafer used as a semiconductor substrate; a step in which the aforementioned wafer is cut in such a way that the aforementioned top surface is larger than the bottom surface for each semiconductor chip; a step in which an adhesive is provided to the top surface of an insulating substrate with a conductive lead formed on the top surface; a step in which the first semiconductor chip obtained as a result of cutting the aforementioned wafer is fixed to the top surface of the aforementioned insulating substrate via the aforementioned adhesive; a step in which the conductive lead on the aforementioned insulating substrate is connected to the electrode pad of the first semiconductor chip with
Masumoto Kenji
Masumoto Mutsumi
Brady III Wade James
Clark S. V.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
Tung Yingsheng
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