Semiconductor device and manufacturing method thereof

Details Semiconductor device and manufacturing method thereof Semiconductor device and manufacturing method thereof

2002-07-25

2003-11-11

Nguyen, Ha (Department: 2812)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C257S751000, C257S758000, C257S767000, C257S775000

Reexamination Certificate

active

06646351

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and manufacturing method thereof, and more particularly, to a semiconductor device employing a fluorine-doped silicon oxide layer as an interconnection insulating layer, and a method of manufacturing the same.
2. Description of the Related Art
In prior art semiconductor devices, SiO
2
layer has been used as an insulating layer to electrically isolate interconnections. Such an SiO
2
layer is primarily produced from source gas, for example, silane (SiH
4
) and tetraethoxysilane (TEOS) by a low pressure or atmospheric pressure chemical vapor deposition (CVD) technique. Particularly, plasma chemical vapor deposition can produce an SiO
2
layer at a low temperature of about 400° C., using TEOS and O
2
, and the SiO
2
layer produced in this way has been widely used. Further, as compared with other thin layer producing methods, the CVD method often uses high purity gas as a reaction source, and provides high quality layers.
However, as microstructure of semiconductor elements has become widespread in recent years, concern about reduction of signal transmission speed has arisen. This implies a problem that reduced interconnection space increases the capacitance between interconnections and reduces signal transmission speed. The reduction in signal transmission speed seems to be one of the negative factors in increasing the performance of semiconductor devices. Therefore, to solve the problem, it is essential to reduce permittivity of the insulating layer formed between interconnections to the lowest possible value.
To reduce the permittivity, in recent years, fluorine-doped silicon oxide or fluorine-doped silicate glass (FSG) has been developed together with the parallel plate CVD technique or high density plasma CVD technique (HDP-CVD). As a method of producing high-density plasma, use of electron cyclotron resonance (ECR) or the inductive coupled plasma (ICP) coil or helicon wave, for example, has been reported.
FIG. 1
shows a sectional view of Cu multi-layer interconnection using a conventional FSG layer. In the same drawing, reference number
81
indicates an FSG layer and likewise,
82
indicates a barrier metal layer,
83
indicates a Cu interconnection in a lower layer,
84
indicates a silicon nitride layer,
85
indicates an FSG layer,
86
indicates another barrier metal layer,
87
indicates a Cu interconnection of an upper layer,
88
indicates another silicon nitride layer and
89
indicates a silicon substrate, respectively. The Cu interconnections
83
and
87
are dual damascene interconnections.
In the FSG layer, as has been reported, the higher the fluorine (F) density, the lower the permittivity, and at the same time, moisture absorption increases. As the moisture absorption of FSG layers
81
and
85
increases, moisture (H
2
O) is taken into these FSG layers. And, H caused by the moisture reacts with F contained in these FSG layers, and HF is liberated from the FSG layers
81
and
85
.
Even if moisture is not taken in, HF is produced from H that is inherently contained in the FSG layer
81
. Furthermore, HF is also produced by reaction of hydrogen (H) and moisture (H
2
O) in silicon nitride layers
84
and
88
with surplus fluorine (F) in FSG layers
81
and
85
. FSG layers
81
and
85
and silicon nitride layers
84
and
88
contain H, because gaseous materials such as silane and ammonia containing H are employed as source gas, and this H is mixed into FSG layers
81
/
85
and silicon nitride layers
84
/
88
.
The above-noted HF will cause corrosion of Cu interconnections
83
/
87
or barrier metal layers
82
/
86
, and degrade adhesion between Cu interconnections
83
/
87
and insulating layers
81
/
84
/
85
/
88
. Further, this corrosion and deteriorated adhesion will cause more serious problems, for example, layer peeling off, bonding durability decline and decrease in reliability.
As described above, it has been proposed to use an FSG layer in interconnections as an insulating layer with low permittivity, to prevent signal transmission delay. However, there is a problem in using an FSG layer, that is, moisture absorption is high and HF is generated, causing corrosion of interconnection itself or barrier metal layer or peeling off of layers. Thus, a semiconductor device employing fluorine-doped silicon oxide as an insulating layer for interconnections and including multi-layer interconnection to decrease the influence of HF, and a method of manufacturing the same have been expected.
BRIEF SUMMARY OF THE INVENTION
A semiconductor device according to a first aspect of the present invention comprises:
a semiconductor substrate;
an interlayer insulating layer formed above the semiconductor substrate;
a first metal interconnection embedded in the interlayer insulating layer with a surface thereof exposed to substantially the same plane as a surface of the interlayer insulating layer;
a diffusion preventive layer formed on at least the metal interconnection to prevent diffusion of a metal included in the first metal interconnection;
a nitrogen-doped silicon oxide layer formed on the diffusion preventive layer;
a fluorine-doped silicon oxide layer formed on the nitrogen-doped silicon oxide layer; and
a second metal interconnection embedded in the fluorine-doped silicon oxide layer with a surface thereof exposed to substantially the same plane as a surface of the fluorine-doped silicon oxide layer, and electrically connected to the first metal interconnection.
A semiconductor device according to a second aspect of the invention comprises:
a semiconductor substrate;
an interlayer insulating layer formed above the semiconductor substrate;
a first metal interconnection embedded in the interlayer insulating layer with a surface thereof exposed to substantially the same plane as a surface of the interlayer insulating layer;
a diffusion preventive layer formed on at least the metal interconnection to prevent diffusion of a metal included in the first metal interconnection;
a first nitrogen-doped silicon oxide layer formed on the diffusion preventive layer;
a fluorine-doped silicon oxide layer formed on the first nitrogen-doped silicon oxide layer;
a second nitrogen-doped silicon oxide layer formed on the fluorine-doped silicon oxide layer; and
a second metal interconnection embedded in the fluorine-doped silicon oxide layer with a surface thereof exposed to substantially the same plane as a surface of the second nitrogen-doped silicon oxide layer, penetrating through the second nitrogen-doped silicon oxide layer, and electrically connected to the first metal interconnection.
A semiconductor device manufacturing method according to a third aspect of the invention comprises:
embedding an under interconnection layer in an interlayer insulating layer such that a surface thereof is exposed to substantially the same plane as a surface of the interlayer insulating layer;
forming a diffusion preventive layer to prevent diffusion of a metal included in the under interconnection layer, on at least the under interconnection layer;
forming a first nitrogen-doped silicon oxide layer on the diffusion preventive layer;
forming a fluorine-doped silicon oxide layer on the nitrogen-doped silicon oxide layer;
forming an interconnection groove and a via hole extending from a bottom of the interconnection groove above the under interconnection layer in the fluorine-doped silicon oxide layer; and
forming a plug in the via hole with a metal layer, to be in electrically contact with the under interconnection layer, and an upper interconnection layer in the interconnection groove with the metal layer, to be electrically contact with the plug.


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Richard Swope

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