Active solid-state devices (e.g. – transistors – solid-state diode – Avalanche diode – With means to limit area of breakdown
Reexamination Certificate
2001-12-11
2003-10-28
Jackson, Jerome (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Avalanche diode
With means to limit area of breakdown
C257S605000, C257S655000
Reexamination Certificate
active
06639301
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a semiconductor device such as a semiconductor diode and its manufacturing method.
2. Description of the Related Art
A voltage regulator diode (a semiconductor diode)
1
shown in
FIG. 1
is known. The semiconductor diode (hereinafter referred as “an earlier semiconductor diode”)
1
has, e.g. a simple three-layer structure stacked in such a way that an n-type semiconductor layer
2
having high impurity concentration, an n-type semiconductor layer
3
and a p-type semiconductor layer
4
having high impurity concentration are stacked sequentially on a silicon substrate. Metal films
5
and
6
to make electrodes are respectively formed on main surfaces of the n-type semiconductor layer
2
and the p-type semiconductor layer
4
.
There exists usually a strong electric field in a depletion layer of a pn junction applied of reverse bias voltage for the earlier semiconductor diode
1
having the above junction structure and the electric field gets stronger locally and susceptible to occur breakdown under influence of impurity elements and ions attached on its surface at a chip side where end portions of the pn junction emerge. Therefore, it can often be hard to gain a reverse breakdown voltage expected theoretically for the earlier semiconductor diode
1
. To reduce the electric field on the chip side, the bevel contour to machine aslant by an appropriate angle to the pn junction interface
9
for reducing the electric field is adopted. By adopting such the bevel contour, the electric field at the chip outer-surface
7
is reduced and breakdown over the whole face of the junction inside the semiconductor is made to occur to stabilize the breakdown behavior. For semiconductor devices having breakdown voltage higher than the voltage regulator diode, it is known that the breakdown voltage can be improved by adopting the bevel structure.
SUMMARY OF THE INVENTION
The earlier semiconductor diode
1
, however, has problems as explained below:
(a) For the earlier semiconductor diode
1
, to protect the chip outer-surface
7
from the effects of outside environment in an assembling process the chip outer-surface
7
is coated with an insulation film
8
as shown in
FIG. 1
after employing wet cleaning by acid or alkali chemicals. However, for the semiconductor diode manufactured in such a way, it is pointed out from the result of product evaluation tests that performance and quality of the product is not stable. The reasons for instability in the performance are given that changes in the surface state and surface failure occur on the chip outer-surface
7
under influence of the wet cleaning or coating of the insulation film
8
. Since the surface state of actual semiconductor chips is very active, it is very difficult to control the precision and reproducibility of such surface state.
(b) The earlier semiconductor diode
1
has the n-type semiconductor layer
3
having impurity concentration much lower than that of the p-type semiconductor layer
4
, and in the case that it can be considered a one-sided abrupt junction, avalanche breakdown voltage at the pn junction part of the n-type semiconductor layer
3
with the p-type semiconductor layer
4
is determined by impurity concentration of the n-type semiconductor layer
3
. Accordingly, it was required to control highly accurately resistivity &rgr; of a semiconductor (silicon) wafer to be used for a product. This means that a semiconductor wafer regulated in a strict specification for the resistivity &rgr; was required to be manufactured by a semiconductor wafer manufacturer under a special order and tested after the delivery. In the past, silicon wafers with a narrow range of 0.01 to 0.03 &OHgr;·cm in resistivity &rgr;—for the n-type silicon, it corresponds with a range of 5×10
18
/cm
3
to 7×10
17
/cm
3
in impurity concentration—were used for the order specification.
(c) For manufacturing of the earlier semiconductor diode
1
, since the chip outer-surface
7
has the bevel structure formed aslant to the pn junction interface, there is a problem that the number of processes required increases since processes such as sandblasting, grinding, polishing or etching are added in order to form the bevel structure.
(d) For the earlier semiconductor diode
1
, since the chips cut from the semiconductor wafer are in a packed state and have its side face inclined aslant to the front and back surfaces of the chips, the device geometry makes it difficult to mount the chip on a jig such as collet in an assembling process.
In view of these situations, it is an object of the present invention to provide a semiconductor device having a desired stable breakdown voltage, preventing occurrence of a local breakdown on a semiconductor (chip) side face where the pn junction emerges.
More specifically, the present invention would provide a semiconductor device and its manufacturing method capable of extending a range of resistivity &rgr; of the semiconductor wafer to be originally prepared for manufacturing and lowering cost for the semiconductor wafer.
Another object of the present invention is to provide a manufacturing method for semiconductor device capable of simplifying or omitting chip surface treatment.
Still another object of the present invention is to provide a semiconductor device and its manufacturing method capable of simplifying production process.
Yet still another object of the present invention is to provide a semiconductor device allowing for favorable handling and favorable loading of the chip into a jig, such as the collet, during the product assembly process.
To achieve the above-mentioned objects, the first aspect of the present invention inheres in a semiconductor device embracing (a) a first semiconductor region of a first conductivity type, defined by a first end surface, a second end surface opposing to the first end surface and a first outer surface connecting the first and second end surfaces; (b) a second semiconductor region of the second conductivity type, defined by a third end surface, a fourth end surface opposing to the third end surface and a second outer surface connecting the third and fourth end surfaces, the fourth end surface is in contact with the first end surface; (c) a third semiconductor region of the first conductivity type connected with the first semiconductor region at the second end surface; (d) a fourth semiconductor region of the second conductivity type connected with the second semiconductor region at the third end surface; and (e) a fifth semiconductor region having inner surface in contact with the first and second outer surfaces and an impurity concentration lower than the first semiconductor region, configured such that the fifth semiconductor region surrounds the first and second semiconductor regions, the fifth semiconductor region is disposed between the third and fourth semiconductor regions. Here, the first conductivity type and the second conductivity type are conductivity types opposite to each other. That is, the second conductivity type is the p-type if the first conductivity type is assigned to be n-type and the second conductivity type is n-type if the first conductivity type is p-type.
According to the semiconductor device of the first aspect of the present invention, the first and the second semiconductor regions are stacked with each other in such a way that they implement a localized pn junction interface (hereinafter referred as “first pn junction interface”). Another pn junction interface (hereinafter referred as “second pn junction interface”) is formed between the fourth semiconductor region and the fifth semiconductor region. Since the impurity concentration of the first semiconductor region is higher than that of the fifth semiconductor region, the first pn junction interface is more susceptible to cause breakdown than the second pn junction interface positioned on the peripheral side of the semiconductor device. Accordingly, since the electrical field on a chip outer-surface of the s
Jackson Jerome
Kilpatrick & Stockton LLP
Sanken Electric Co. Ltd.
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