Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Reexamination Certificate
2001-12-05
2003-09-23
Flynn, Nathan J. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
C257S701000, C257S750000, C257S751000, C257S768000, C257S769000, C257S773000, C257S774000, C257S775000
Reexamination Certificate
active
06624514
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2000-371011, Dec. 6, 2000, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and manufacturing method thereof, and particularly to a semiconductor device having a wiring structure formed by a buried wiring technique, and manufacturing method thereof.
2. Description of the Related Art
Jpn. Pat. Appln. KOKAI Publication No. 2000-77407 discloses an example of a semiconductor device and manufacturing method thereof, using a conventional “buried wiring” (which can be referred to as a metal damascene wiring) technique. In this example, wiring portions having different thicknesses are suitably disposed in accordance with relationships relative to neighboring wiring and so forth, to reduce wiring resistance or inter-wiring capacitance.
BRIEF SUMMARY OF THE INVENTION
According to a first aspect of the present invention, there is provided a semiconductor device comprising:
a semiconductor substrate;
a middle inter-level insulating film disposed on or above the semiconductor substrate;
a conductive layer disposed on the middle inter-level insulating film;
an upper inter-level insulating film disposed on the middle inter-level insulating film and the conductive layer, the upper inter-level insulating film including first, second, and third wiring grooves distant from each other, the second and third wiring grooves using the conductive layer as their bottoms;
in-groove barrier layers covering side surfaces of the first, second, and third wiring grooves; and
first, second, and third wiring layers buried in the first, second, and third wiring grooves, the first, second, and third wiring layers being derived from the same wiring film, the first, second, and third wiring layers having a thickness larger than that of the conductive layer, the second and third wiring layers being electrically connected to the conductive layer.
According to a second aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising:
forming a lower wiring layer on a lower inter-level insulating film disposed on or above a semiconductor substrate;
forming an inter-level barrier layer on the lower inter-level insulating film and the lower wiring layer,
forming a middle inter-level insulating film on the inter-level barrier layer;
forming a conductive film on the middle inter-level insulating film;
patterning the conductive film by photo-lithography to form a conductive layer having a predetermined pattern from the conductive film;
forming an upper inter-level insulating film on the middle inter-level insulating film and the conductive layer;
patterning the upper inter-level insulating film by photo-lithography to form first, second, and third wiring grooves distant from each other in the upper inter-level insulating film, the second and third wiring grooves using the conductive layer as their bottoms;
forming a via-hole extending from the first wiring groove to the lower wiring layer in the middle inter-level insulating film and the inter-level barrier layer,
forming a barrier film to cover a region including the via-hole, the first, second, and third wiring grooves;
forming a wiring film on the barrier film to fill the via-hole, the first, second, and third wiring grooves; and
planarizing a resultant structure with the wiring film thus formed, by chemical mechanical polishing, to partly remove the barrier film and the wiring film until the upper inter-level insulating film is exposed, and to leave via-plug, first, second, and third wiring layers in the via-hole, the first, second, and third wiring grooves, respectively.
REFERENCES:
patent: 5877075 (1999-03-01), Dai et al.
patent: 6008084 (1999-12-01), Sung
patent: 6100177 (2000-08-01), Noguchi
patent: 6124638 (2000-09-01), Iwasa
patent: 6177347 (2001-01-01), Liu et al.
patent: 6417116 (2002-07-01), Kudo et al.
patent: 2002/0027287 (2002-03-01), Takagi et al.
Flynn Nathan J.
Greene Pershelle
Kabushiki Kaisha Toshiba
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