Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Insulative housing or support
Reexamination Certificate
2000-05-25
2002-06-25
Nguyen, Tuan H. (Department: 2813)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Insulative housing or support
C438S108000, C257S778000, C361S748000, C361S760000, C361S770000
Reexamination Certificate
active
06410366
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a semiconductor device and method of manufacture thereof, to a circuit board, and to an electronic instrument.
TECHNICAL ART
In recent years, with the increasing compactness of electronic instruments, semiconductor device packages adapted to high density mounting are in demand. In response to this, surface mounting packages such as BGA (Ball Grid Array) and CSP (Chip Scale/Size Package) have been developed. Such packages have been applied, for example, to the packaging of semiconductor chips such as DRAM or synchronous DRAM in which a plurality of electrodes is arranged in a row. More specifically, a semiconductor chip and the substrate on which an interconnect pattern is formed are disposed spaced apart, and leads forming a part of the interconnect pattern are bent and bonded to the semiconductor chip electrodes.
According to this construction, the bonding must be carried out for each single lead, and therefore when the spacing between electrodes is small, a precision bonding process is required, and this is difficult to support.
DISCLOSURE OF THE INVENTION
The present invention solves this problem, and has as its objective the provision of a compact semiconductor device which uses a semiconductor chip having electrodes disposed in a row and method of manufacture thereof, a circuit board, and an electronic instrument.
(1) A semiconductor device of the present invention comprises:
a semiconductor chip which is subjected to face-down bonding, having a plurality of electrodes aligned to be concentrated on a straight line;
a substrate, superposed on the semiconductor chip, on which is formed an interconnect pattern having bonding portions to which the electrodes of the semiconductor chip are connected and lands electrically connected to the bonding portions; and
at least one support provided between the semiconductor chip and the substrate;
wherein using the connected electrodes and bonding portions and the support, the substrate superposed on the semiconductor chip is maintained substantially parallel to the semiconductor chip.
According to the present invention, the plurality of electrodes are aligned concentrated on a straight line, and the semiconductor chip which would not be stable with the electrodes and bonding portions alone, is maintained parallel to the substrate by the support. Therefore, the lateral sides of the semiconductor chip contacting the interconnect pattern formed on the substrate and making an electrical connection is prevented. Furthermore, bending of the substrate can be prevented.
Since the semiconductor chip is subjected to face-down bonding, the bonding is carried out within the area of the semiconductor chip. Therefore, the area of the substrate can be reduced to the minimum necessary. As a result, the semiconductor device can be made more compact.
(2) A semiconductor device of the present invention comprises:
a semiconductor chip which is subjected to face-down bonding, having a plurality of electrodes aligned to be concentrated in the vicinity of a straight line;
a substrate superposed on the semiconductor chip on which is formed an interconnect pattern having bonding portions to which the electrodes of the semiconductor chip are connected and lands electrically connected to the bonding portions; and
at least one support provided between the semiconductor chip and the substrate;
wherein using the connected electrodes and bonding portions and the support, the substrate superposed on the semiconductor chip is maintained substantially parallel to the semiconductor chip.
According to the present invention, a plurality of electrodes are aligned concentrated in the vicinity of a straight line, and the semiconductor chip which would not be stable with the electrodes and bonding portions alone is maintained parallel to the substrate by the support. Therefore, the lateral sides of the semiconductor chip contacting the interconnect pattern formed on the substrate and making an electrical connection is prevented. Furthermore, bending of the substrate can be prevented.
Since the semiconductor chip is subjected to face-down bonding, the bonding is carried out within the area of the semiconductor chip. Therefore, the area of the substrate can be reduced to the minimum necessary. As a result, the semiconductor device can be made more compact.
(3) The semiconductor device may further comprise external electrodes connected to the lands.
Since the semiconductor chip and substrate and are maintained parallel, stress applied from the external electrodes is transmitted in a balanced way, and concentration of stress can be prevented.
(4) In this semiconductor device, the support may be provided in a position distanced from the straight line on which the electrodes are concentrated.
By positioning the support in this way, a polygon being at least a triangle is formed by joining the bonded electrodes and bonding portions and the support, and the semiconductor chip and substrate can be maintained parallel.
(5) In this semiconductor device, with the semiconductor chip conceived as divided into two regions by a notional center line, the support may be provided in the region on the opposite side from the region in which the external electrodes are provided.
(6) In this semiconductor device, the electrodes may be provided in a center portion of the semiconductor chip, and the support may be formed in a peripheral portion of the semiconductor chip.
(7) In this semiconductor device, a plurality of the supports may be provided, and the distance between adjacent of the supports may be formed to be larger than the distance between adjacent of the electrodes.
(8) In this semiconductor device, the support may take approximately the same flat shape as the electrodes.
Since the support can be provided close to a point in form, it may be squashed down to adjust the height.
(9) In this semiconductor device, the support may be formed in a position distanced from the lands.
Since the support is provided in a position distanced from the external electrodes, even if the contact portion of the support on the substrate is bent, the uniformity of height (coplanarity) of the external electrodes can be assured.
(10) In this semiconductor device, the support may be formed of an electrically insulating material.
By this means, electrical connection between the semiconductor chip and the interconnect pattern of the substrate can be prevented.
(11) In this semiconductor device, the support may be formed by bonding first bumps formed on the semiconductor chip of the same material as the electrodes and distanced from the electrodes and second bumps formed on the substrate of the same material as the interconnect pattern and distanced from the interconnect pattern.
The first bumps can be formed at the same time as the electrodes, and the second bumps can be formed at the same time as the interconnect pattern, thus avoiding an increase in the number of manufacturing processes.
(12) In this semiconductor device, the electrodes of the semiconductor chip may be connected to the bonding portions through an anisotropic conductive material formed of conductive particles dispersed within an adhesive.
Since the bonding portions and electrodes are electrically connected by the anisotropic conductive material, a connection of excellent reliability is obtained.
(13) A method of manufacturing a semiconductor device of the present invention comprises:
a step of providing a semiconductor chip having a plurality of electrodes aligned to be concentrated on a straight line;
a step of providing a substrate on which is formed an interconnect pattern having bonding portions formed in positions corresponding to the electrodes of the semiconductor chip, and lands electrically connected to the bonding portions;
a step of subjecting the semiconductor chip to face-down bonding to connect the electrodes to the bonding portions; and
a step of providing at least one support between the semiconductor chip and the substrate, of approximately the same height as the total thickness of th
Berezny Nema
Nguyen Tuan H.
Oliff & Berridg,e PLC
Seiko Epson Corporation
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