Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified configuration
Reexamination Certificate
2000-04-18
2002-09-17
Everhart, Caridad (Department: 2825)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified configuration
C257S773000, C257S734000, C257S750000, C257S751000, C257S758000
Reexamination Certificate
active
06452277
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor devices and manufacturing methods thereof, and more particularly, to a manufacturing method of a semiconductor device which ensures a good electrical connection of metal interconnections, and a semiconductor device obtained by the mentioned manufacturing method.
2. Description of the Background Art
In recent years, as semiconductor devices represented by ULSIs have become more integrated and more powerful, complexity and density of structures especially interposed in the vertical direction between metal interconnections have been increasing. A conventional method of manufacturing a semiconductor device having metal interconnections will now be described by way of example.
Referring first to
FIG. 32
, a polycrystalline silicon (hereinafter, referred to as “polysilicon”) plug
104
is formed on a semiconductor substrate (not shown). A silicon oxide film
103
is formed on the semiconductor substrate to cover polysilicon plug
104
. A prescribed photo resist pattern (not shown) is formed on silicon oxide film
103
.
Using the photo resist pattern as a mask, silicon oxide film
103
is subjected to anisotropic etching to form a contact hole
105
exposing the surface of polysilicon plug
104
. The photo resist pattern is then removed.
Next, a barrier metal
106
including a titanium nitride film is formed by sputtering. At this time, barrier metal
106
formed on the upper surface of silicon oxide film
103
and on the side and bottom surfaces of contact hole
105
has approximately the same film thickness ti.
Next, a metal film
107
including tungsten is formed by sputtering or the like to cover barrier metal
106
. A prescribed photo resist pattern
132
is formed on metal film
107
.
Referring next to
FIG. 33
, metal film
107
is subjected to anisotropic etching using photo resist pattern
132
as a mask, to expose the surface of barrier metal
106
located on the upper surface of silicon oxide film
103
.
Referring next to
FIG. 34
, the exposed barrier metal
106
is further anisotropically etched using photo resist pattern
132
as a mask, so that the upper surface of silicon oxide film
103
is exposed. Thereafter, photo resist pattern
132
is removed. A metal interconnection
107
a
is thus formed from metal film
107
.
Next, an interlayer insulating film (not shown) is further formed on silicon oxide film
103
to cover metal interconnection
107
a
. Accordingly, a main portion of the semiconductor device having the metal interconnection is completed.
The above-described method of manufacturing a semiconductor device, however, exhibits the following problems. At the step shown in
FIG. 34
, after the etching of barrier metal
106
for the film thickness ti, over-etching is conducted such that no etch residue of barrier metal
106
is left on the upper surface of silicon oxide film
103
.
This over-etching may cause barrier metal
106
located on the side surface of contact hole
105
to be etched away, which leads to exposure of the surface of polysilicon plug
104
. Thereafter, the semiconductor substrate is processed with HCl or NH
4
OH to remove metal contamination or dust particles thereon.
At this time, if the cleaning with NH
4
OH is performed with the surface of polysilicon plug
104
being exposed, isotropic etching will proceed from the exposed portion of polysilicon plug
104
as shown in
FIG. 35
, so that a concave portion
120
is formed. If the interlayer insulating film (not shown) is formed in this situation, the concave portion
120
will become a void.
This void may cause an unstable electrical connection between metal interconnection
107
a
, barrier metal
106
and polysilicon plug
104
. Further, metal interconnection
107
a
and barrier metal
106
may be disconnected from polysilicon plug
104
. As a result, the operation of the semiconductor device would become unstable, hindering a desired operation.
SUMMARY OF THE INVENTION
The present invention is directed to solve the above problems. One object of the present invention is to provide a manufacturing method of a semiconductor device having metal interconnections ensuring a stable electrical connection. Another object of the present invention is to provide a semiconductor device obtained by such a manufacturing method.
A manufacturing method of a semiconductor device according to a first aspect of the present invention includes the following steps: the step of forming a conductive region on a semiconductor substrate; the step of forming an insulating film on the semiconductor substrate to cover the conductive region; the step of forming a hole in the insulating film to expose a surface of the conductive region; the step of forming a conductive layer in the hole, that is electrically connected to the conductive region exposed at the bottom of the hole; and the step of forming a conductive portion by etching the conductive layer. At the step of forming the conductive portion, an etch rate of the conductive layer is set smaller at least in the vicinity of the side surface of the open end of the hole than in the other portion, to prevent the exposure of the surface of the conductive region at the bottom of the hole.
According to this manufacturing method, at the step of forming the conductive portion, the exposure of the surface of the conductive region at the bottom of the hole is prevented particularly taking advantage of an RIE-lag effect. Thus, even if processing with NH
4
OH is conducted in a later step for removal of metal contamination or dust particles on the semiconductor substrate, the conductive region is prevented from being etched. As a result, it is possible to accomplish a semiconductor device in which a good electrical connection between the conductive portion and the conductive region is ensured. The RIE-lag effect will be described below in conjunction with embodiments of the present invention.
Preferably, the step of forming the conductive layer includes: the step of forming a first conductive layer having a film thickness smaller on the side surface of the hole than on the upper surface of the insulating film or on the bottom surface of the hole; and the step of forming a second conductive layer having an etch characteristic different from that of the first conductive layer, to cover the first conductive layer. The step of forming the conductive portion preferably includes: the step of forming a mask material, on the second conductive layer, having a diameter smaller than the aperture of the hole at its open end; the step of anisotropically etching the second conductive layer using the mask material as a mask, to expose the surface of the first conductive layer located on the upper surface of the insulating film; and the step of further anisotropically etching the exposed first conductive layer using the mask material as a mask, to remove the first conductive layer located on the upper surface of the insulating film and the first conductive layer located between the side surface of the hole and the second conductive layer.
In this case, when the first conductive layer located between the side surface of the hole and the second conductive layer is subjected to etching, the first conductive layer formed on the side surface of the hole is thinner than the first conductive layer formed in the other portions. This prevents sufficient etchant from entering the narrow portion as the etching proceeds, so that the etch rate of the first conductive layer in this portion becomes smaller than that in the other portions. Accordingly, at the time of anisotropic etching of the first conductive layer, it is possible to reliably prevent the exposure of the conductive region even if over-etching is conducted.
Preferably, the step of forming the hole includes the step of shaping the hole such that the hole has a bowing or upwardly tapering cross section.
In this case, the first conductive layer can readily be formed by sputtering, for example, to have a film thickness smaller on the side surface
Tabaru Kenji
Teratani Akemi
Yokoi Takahiro
Yoshikawa Kazunori
Everhart Caridad
Luu Chuong
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
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