Semiconductor device and manufacturing method thereof

Active solid-state devices (e.g. – transistors – solid-state diode – Physical configuration of semiconductor – With specified crystal plane or axis

Reexamination Certificate

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Details

Other Related Categories

C257S628000, C257S347000

Type

Reexamination Certificate

Status

active

Patent number

08008751

Description

ABSTRACT:
A semiconductor device includes an insulator layer, and an n-channel MIS transistor having an n channel and a pMIS transistor having a p channel which are formed on the insulator layer, wherein the n channel of the n-channel MIS transistor is formed of an Si layer having a uniaxial tensile strain in a channel length direction, the p channel of the p-channel MIS transistor is formed of an SiGe or Ge layer having a uniaxial compressive strain in the channel length direction, and the channel length direction of each of the n-channel MIS transistor and the p-channel MIS transistor is a <110> direction.

REFERENCES:
patent: 2001-160594 (2001-06-01), None
patent: 2005-039171 (2005-02-01), None
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U.S. Appl. No. 11/705,450, filed Feb. 13, 2007.
U.S. Appl. No. 11/437,730, filed May 22, 2006.
U.S. Appl. No. 11/369,662, filed Feb. 21, 2003.
U.S. Appl. No. 10/188,824, filed Jul. 5, 2002.
Irisawa, et al., “High Current Drive Uniaxially-Strained SGOI pMOSFETs Fabricated by Lateral Strain Relaxation Technique”, pp. 178-179, 2005 Symposium on VLSI Technology Digest of Technical Papers.
Lei, et al., “Strain relaxation in patterned strained silicon directly on insulator structures”; 2005 American Institute of Physics, pp. 251926-1251926-3.
Irie, et al., “In plane mobility anisotropy and universality under uni-axial strains in n- and p-MOS inversion layers on(100), (110), and (111)Si”, IEDM, Jan. 2004, pp. 9.5.1-9.5.4.
Chan, et al.,Fabrication and mobility characteristics of ultra-thin strained Si directly on Insulator(SSDOI)MOSFETs, IEDM, May 2003, pp. 3.1.1-3.1.4.
Tezuka, et al., “A novel fabrication technique of ultrathin and relaxed SeGe buffer layers with High Ge fraction for Sub-100 nm Strained silicon-on-insulator MOSFETs”, 2000, pp. 2866-2874.
Choi, et al, “Sub-20nm CMOS FinFET Technologies”, IEEE, Mar. 2001, pp. 19.1.119.1.4.
Irisawa, et al., “Electron Transport Properties of Ultrathin-body and Tri-gate SOI nMOSFETs with Biaxial and Uniaxial Strain”, IEEE, 2006, 4 pps.
Irisawa, et al., “High performance multi-gate pMOSFETs using uniaxially-strained SGOI channels”, IEEE, 2005, 4 pps.
Uchida, et al., “Physical Mechanisms of electron mobility enhancement in uniaxial stressed MOSFETs and impact of uniaxial stress engineering in ballistic regime”, IEEE, Aug. 2005, 4 pps.

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