Semiconductor device and manufacturing method therefor

Details Semiconductor device and manufacturing method therefor Semiconductor device and manufacturing method therefor

2002-06-28

2004-05-18

Fourson, George (Department: 2823)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

C438S431000, C438S432000

Reexamination Certificate

active

06737336

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method therefor, and more particularly, to an isolation structure of a semiconductor device.
2. Description of Related Art
Trench isolation is one method of isolating and insulating semiconductor elements from one another. A trench isolation structure is formed by forming a trench in the surface of a semiconductor substrate, and by filling the trench with a polysilicon film or a silicon oxide film. Compared with other insulation and isolation structures, the trench isolation structure requires a much smaller area and involves much lower parastic capacitance. Therefore, the trench isolation structure is suitable for increasing the density of and the operating speed of a semiconductor device.
FIG. 29
is a cross-sectional view of a conventional MOS semiconductor device having a trench isolation structures. In the drawing, reference numeral
101
designates a semiconductor substrate;
102
designates a trench;
104
designates a buried film;
105
designates a gate insulating film;
106
designates a polysilicon layer;
107
designates a metal silicide layer;
108
designates a sidewall;
109
designates a silicon oxide film;
1010
and
1011
designate source/drain regions;
1012
designates an interlayer insulating film; and
1013
designates a gate electrode. The gate electrode
1013
is formed from the polysilicon layer
106
and the metal silicide layer
107
. An isolation region is formed from a trench isolation structure comprising the trench
102
, the silicon oxide film
109
, and the buried film
104
.
Japanese Patent Application Laid-open Nos. 4-209551 and 2-114654 disclose a structure which is formed by filling an trench isolation with a polysilicon film and capping a surface of the trench isolation by thermal oxidation. As can be seen from
FIG. 29
, in the MOS semiconductor device, the gate electrode
1013
runs over the trench isolation structure and is shared among a plurality of transistors. Therefore, the buried film
104
must be formed from a silicon oxide film having a highly-insulating characteristic.
FIG. 30
is a cross-sectional view of a trench isolation structure of a conventional semiconductor device. In the drawing, reference numeral
110
designates what is called a bird's beak.
Silicon oxide films include several types of films; among them a silicon oxide film formed by thermal oxidation (hereinafter referred to as a “thermal oxide film”) and a silicon oxide film (hereinafter referred to as a “CVD silicon oxide film) formed by CVD (Chemical Vapor Deposition). The thermal oxide film is formed by forming the trench
102
in the surface of the semiconductor substrate
101
and subjecting the substrate to a heat treatment for a long period of time. As a result, the bird's beak
110
becomes larger, as shown in FIG.
30
. In contrast, the CVD silicon oxide film retards formation of the bird's beak and is suitable for miniaturizing a semiconductor element. A semiconductor device for which a trench isolation structure is formed through use of a CVD silicon oxide film is disclosed in Japanese Patent Application Laid-open Nos. 59-135743 and 63-266878.
A method of manufacturing a semiconductor device having a trench isolation structure through use of a CVD silicon oxide film will now be described.
FIGS. 31
to
34
are cross-sectional views showing a process of manufacturing a conventional semiconductor device, and
FIG. 34
is a cross-sectional view of a trench isolation structure of the conventional semiconductor device. In
FIG. 31
, reference numeral
1021
designates a silicon nitride film; and
1091
designates a silicon oxide film.
First, the silicon oxide film
1091
and the silicon nitride film
1021
are formed on the semiconductor substrate
101
. Through use of a photoresist mask (not shown), the silicon nitride film
1021
is patterned in such a way as to open an area where the trench
102
is to be formed.
FIG. 31
is a cross-sectional view of an element of a semiconductor device obtained after completion of the foregoing processing operations.
Next, after the silicon oxide film
1091
and the semiconductor substrate
101
have been etched while the silicon nitride film
1021
is used as a mask, the inner wall of the trench
102
is subjected to thermal oxidation, thereby forming the silicon oxide film
109
.
FIG. 32
is a cross-sectional view of the element of the semiconductor device obtained after completion of the foregoing operations.
In
FIG. 33
, reference numeral
1041
designates a CVD silicon oxide film. As seen in the drawing, the trench
102
is filled with the CVD silicon oxide film
1041
, and the substrate is then subjected to heat treatment at 1000° C. in an oxygen atmosphere for about one hour.
FIG. 33
is a cross-sectional view of the element of the semiconductor device obtained after completion of the foregoing processing operations.
After the silicon substrate has been made smooth by means of CMP (Chemical Mechanical Polishing), the silicon nitride film
1041
and the silicon oxide film
1091
are removed, thereby completing the trench isolation structure.
Since the CVD silicon oxide film has a low density, mere embedding of the film into the trench results in a poor-quality CVD silicon oxide film; the silicon oxide film assumes particularly poor quality in the center of the trench
102
. As a result, the CVD silicon oxide film
1041
is etched when the silicon oxide film
1091
and other silicon oxide films are removed by hydrofluoric acid, thereby forming a recess in the CVD silicon oxide film
1041
such as that shown in FIG.
34
. For this reason, after deposition of the CVD silicon oxide film
1041
, the substrate is subjected to heat treatment so as to improve the etch resistance characteristics of the CVD silicon oxide film
1041
, thereby preventing formation of a recess.
The semiconductor device shown in
FIG. 29
is formed by sequentially forming the gate insulation film
105
, the gate electrodes
1013
, the source/drain regions
1010
and
1011
, and the sidewalls
108
.
Since the CVD silicon oxide is formed in such a manner as mentioned above, formation of a bird's beak is retarded when compared with the case in which a buried film is formed from a thermal oxide film. Consequently, the CVD silicon oxide film is suitable for miniaturizing a semiconductor element.
However, in the conventional semiconductor device, if the substrate is subjected to heat treatment in order to improve the quality of the CVD silicon oxide film after the CVD silicon oxide film was formed, or if the substrate is subjected to heat treatment during the process of fabrication of an element, for reasons of a difference in coefficient of thermal expansion between the CVD silicon oxide film and the semiconductor substrate, the volume of the CVD silicon oxide film filled in the trench is changed to exert mechanical stress (stress) in an area between the semiconductor substrate and a buried layer. The stress induces defects in the semiconductor substrate around the trenches. If such a semiconductor substrate is subjected to heat treatment in an oxygen atmosphere, the CVD silicon oxide film expands, as a result of which defects become particularly noticeable.
FIG. 35
is a cross-sectional view of an element of a conventional semiconductor device and shows an NMOS when a leakage current flows because of defects. In the drawing, reference numeral
120
designates a defect;
130
designates an electron; and
140
designates a hole. Because of the semiconductor device being subjected to the heat treatment after deposition of the CVD silicon oxide film, the defect
120
is formed in the semiconductor substrate around the trench. The defect
120
deteriorates the reliability of the element, in addition to causing the electron
130
and the hole
140
to form a pair. As a result of migration of the electron
130
and the hole
140
in the directions indicated by arrows in the drawing, a leakage current f

Affiliated with

Also associated with

Rating

Semiconductor device and manufacturing method therefor does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor device and manufacturing method therefor, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device and manufacturing method therefor will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3222953