Semiconductor device and manufacturing method of the same

Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Including means for establishing a depletion region...

Reexamination Certificate

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C257S134000, C257S139000, C257S256000, C257S272000, C257SE29014, C257SE29063, C257SE29127, C257SE29255, C257SE29265, C257SE29312, C257SE29314, C257SE21403, C257SE21408, C438S186000

Reexamination Certificate

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07944017

ABSTRACT:
An n type impurity region is continuously formed on the bottom portion of a channel region below a source region, a gate region and a drain region. The n type impurity region has an impurity concentration higher than the channel region and a back gate region, and is less influenced by the diffusion of p type impurities from the gate region and the back gate region. Moreover, by continuously forming the impurity region from a portion below the source region to a portion below the drain region, the resistance value of a current path in the impurity region is substantially uniformed. Therefore, the IDSS is stabilized, the forward transfer admittance gm and the voltage gain Gv are improved, and the noise voltage Vno is decreased. Furthermore, the IDSS variation within a single wafer is suppressed.

REFERENCES:
patent: 6306691 (2001-10-01), Koh
patent: 2004/0065896 (2004-04-01), Sakamoto
patent: 2009/0168508 (2009-07-01), Kapoor et al.
patent: 60-92659 (1985-05-01), None
patent: 5-315549 (1993-11-01), None
patent: 8-227900 (1996-09-01), None
patent: 2002-190480 (2002-07-01), None
Korean Office Action dated Jun. 1, 2010, directed to counterpart Korean Application No. 10-2008-0075981; 2 pages.

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