Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Reexamination Certificate
2009-05-08
2010-12-07
Soward, Ida M (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
C257S211000, C257S759000, C257S760000, C257SE21016, C257SE21017, C257SE21018, C257SE21019, C257SE21020, C257SE21021, C257SE21507, C257SE21575, C257SE21576, C257SE21577, C257SE21579, C257SE21584, C257SE21627, C257SE21641
Reexamination Certificate
active
07847405
ABSTRACT:
In one aspect of the present invention, a semiconductor device may include an inter-wiring dielectric film in which a wiring trench is formed, a metal wiring layer formed in the wiring trench in the inter-wiring dielectric film, a first barrier layer formed on a side surface of the wiring trench, the first barrier layer being an oxide film made from a metal different from a main constituent metal element in the wiring layer, a second barrier layer formed on a side surface of the wiring layer, the second barrier layer having a Si atom of the metal used in the wiring layer, and a gap formed between the first barrier layer and the second barrier layer.
REFERENCES:
patent: 6150270 (2000-11-01), Matsuda et al.
patent: 6661094 (2003-12-01), Morrow et al.
patent: 7067418 (2006-06-01), Huang et al.
patent: 7196423 (2007-03-01), Wu et al.
patent: 7345352 (2008-03-01), Matsumura et al.
patent: 7408693 (2008-08-01), Kissa et al.
patent: 2007/0001307 (2007-01-01), Usui et al.
patent: 2007/0018329 (2007-01-01), Oh et al.
patent: 2007/0035032 (2007-02-01), Tsumura et al.
patent: 2008/0179753 (2008-07-01), Won et al.
patent: 2008/0246155 (2008-10-01), Hayashi et al.
patent: 2009/0142919 (2009-06-01), Noguchi et al.
Self-Formed Barrier Technology using CuMn Alloy Seed for Copper Dual-Damascene Interconnect with porous-SiOC/porous-PAr Hybrid Dielectric, T. Watanabe, et al., Jun. 4, 2007.
Conference Proceedings AMC XXII © 2007 Materials Research Society, High Performance Ultra-Low-k (k=2.0/keff=2.4) Hybrid Dielectric/Cu Dual-Damascene Interconnects with Selective Barrier Layer for 32 nm-node, Y. Hayashi, et al. Oct. 17, 2006, p. 263-269.
U.S. Appl. No. 12/332,583, filed Dec. 11, 2008, Watanabe, et al.
Hayashi Yumi
Usui Takamasa
Watanabe Tadayoshi
Kabushiki Kaisha Toshiba
Oblon, Spivak McClelland, Maier & Neustadt, L.L.P.
Soward Ida M
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