Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Assembly of plural semiconductive substrates each possessing...
Reexamination Certificate
2001-08-28
2003-12-30
Graybill, David E. (Department: 2827)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Assembly of plural semiconductive substrates each possessing...
C438S111000, C438S112000, C438S113000, C264S272170
Reexamination Certificate
active
06670220
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a technique of fabricating resin-molded semiconductor devices by using leadframes, and more particularly to a technique suitable for fabricating non-leaded semiconductor device packages having a structure in which external electrode terminals are exposed on a mounting face thereof instead of sidewise lead protrusion, such as small outline non-leaded (SON) packages and quad flat non-leaded (QFN) packages.
2. Description of the Related Art
Leadframes, produced by forming a metal sheet into a desired pattern through fine blanking or etching, are used in fabrication of resin-molded semiconductor devices. Each leadframe unit portion comprises a tab, which is a pad part for mounting a semiconductor chip, and a plurality of leads having tip ends (inner ends) thereof disposed spacedly around the tab. The tab is supported by tab suspension leads extending from frame parts of the leadframe.
In fabrication of resin-molded semiconductor devices by using leadframes such as mentioned above, a semiconductor chip is secured on the tab of each leadframe unit portion, conductive wires are connected between electrodes of the semiconductor chip and the tip ends of the leads, and then the inner lead area including the conductive wires and the semiconductor chip is sealed with resin to form a package for encapsulation. In this process, unnecessary leadframe parts including any protruding parts of leads and tab suspension leads are cut and removed from the package.
According to a known practice in resin-molded semiconductor device fabrication using leadframes, single-sided molding is made on one side of each leadframe unit portion to form a package having a structure in which external electrode terminals (leads) are exposed on a mounting face thereof while no lead protrusion from the periphery thereof is made. This type of semiconductor device package includes an SON package in which leads are exposed along two side edges of a mounting face thereof and a QFN package in which leads are exposed along four side edges of a mounting face thereof in a quadrangular form.
In Japanese Unexamined Patent Publications No. H10 (1998)-34699 and No. H10 (1998)-70217, there are disclosed fabrication techniques for SON packages. In the former, it has been proposed to provide a technique in which a metal mold is covered with an elastic, heat-resistant release film to prevent occurrence of resin burrs at resin sealing in semiconductor device fabrication. In the latter, it has been proposed to provide a technique in which a groove having a cross-sectional shape of an approximately circular arc is formed on a lead-to-lead surface area of mold resin for elongation of a lead-to-lead insulation distance and for prevention of occurrence of resin burrs on a surface where leads are exposed.
Further, Japanese Unexamined Patent Publication No. H10 (1998)-270603 discloses an area-package-type semiconductor device and a method of fabrication thereof. According to this disclosure, as in fabrication of ball-grid-array semiconductor devices, a semiconductor chip is secured on the surface side of a substrate (resin substrate made of glass epoxy resin or the like), external electrodes are disposed in a grid form on the back side thereof, and the semiconductor chip on the surface side is covered with a resin package part. A plurality of area-package-type semiconductor devices are provided in a row on each substrate.
For preventing the external electrodes from being flawed when the substrates are stacked one on top of another, protrusion parts higher than the height of the resin package part are provided on substrates at two or more corners. Thus, the external electrodes will not come into contact with a resin package part of another semiconductor device at the lower position.
For protecting the external electrodes at the time of substrate stacking, it is required to form at least two protrusion parts crosswise with respect to the longitudinal substrate direction.
Non-leaded semiconductor device packages fabricated by single-sided molding, including SON and QFN packages, are used to meet requirements for reduction in physical size and elimination of deformation of external electrode terminal leads.
Since the terminal exposure side of the non-leaded semiconductor device package is used for mounting, the mounting area thereof is smaller than that of a semiconductor device package of a sidewise lead protrusion type, such as a small outline package (SOP) or a quad flat package (QFP). Therefore, on the non-leaded semiconductor device package, if foreign matter adheres to the leads (external electrode terminals) or the leads are flawed, the mounting reliability thereof is degraded.
Referring to
FIGS. 34
,
35
and
36
, there are shown schematic diagrams of mounting conditions in which a non-leaded semiconductor device
1
is mounted on a wiring board
50
such as a mother board. A lead (external electrode terminal)
4
exposed on a mounting face
3
of a package part
2
of the non-leaded semiconductor device
1
is bonded to a land
52
on the wiring board
50
via a bonding material (solder)
51
. On a surface part of the lead
4
(mounting surface), a plating film
54
is provided to enhance the wettability of solder (solderability). In these figures, the plating film
54
is indicated as a solid thick line. The plating film
54
is formed by Pb—Sn soldering or palladium-plating (for avoiding the use of Pb as a soldering material).
In pre-plating, a palladium plating film is formed on a leadframe in advance. In post-plating, the soldering film
54
is formed after molding. In soldering film formation, solder is used as a soldering material. In palladium plating film formation, an alloy material not containing Pb, such as Sn—Zn or Sn—Ag, is used.
FIG. 34
shows a normal mounting condition in which no abnormality is found in mounting. For example, the solder
51
is formed over the entire mounting surface of the lead
4
, and a fillet
55
is formed adequately on the outer end face of the lead
4
. In visual inspection, it can be judged that the solderability is good.
As shown in
FIG. 35
, if a foreign substance
56
adheres to the exposure surface of the lead
4
, electrical connection is not provided at a region having the foreign substance
56
, which could cause poor continuity.
As shown in
FIG. 36
, if the exposure surface of the lead
4
is flawed to cause partial missing of the plating film
54
, the solder
52
is not formed at a region having no plating film. In this condition, poor continuity is prone to occur due to a decrease in bonding area. In the example shown in
FIG. 36
, since the region having no plating film due to a flaw on the exposure surface of the lead
4
is located at the outer end side, a fillet is not formed adequately. In visual inspection, it is therefore possible to check for poor bonding. If the exposure surface of the lead
4
is flawed at the inner side thereof, a region having no plating film cannot be detected in visual inspection, i.e., a check for poor continuity cannot be made. This could cause degradation in mounting reliability.
As can be seen from the above, in fabrication of non-leaded semiconductor devices, it is required to prevent partial missing of a plating film due to a foreign substance or a flaw on a mounting surface of any lead.
At the workplace of the inventors, non-leaded semiconductor device packages such as QFN and SON packages are manufactured using metallic matrix-type leadframes. The matrix-type leadframe comprises a plurality of unit patterns (unit leadframe patterns) which are arranged on a plurality of rows and columns in a matrix form. On each unit leadframe pattern of the matrix-type leadframe, one non-leaded semiconductor device is formed. More specifically, a semiconductor chip is secured on the center part of each unit leadframe pattern, conductive wires are bonded between electrodes of the semiconductor chip and the inner ends of leads, and then single-sided molding is made on the se
Ito Youkou
Saga Toru
Sakuraba Tadaki
Takeshima Hidehiro
Tamai Yoshiaki
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