Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
2006-07-18
2006-07-18
Tran, Henry N. (Department: 2674)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S213000, C716S030000
Reexamination Certificate
active
07079104
ABSTRACT:
A semiconductor device that operates with reduced power consumption having a clock transfer blocking circuit and an external data transfer blocking circuit that blocks a clock signal and a data signal from being transferred to a data output circuit when a data signal captured by a data capturing circuit is to be latched by a latch circuit. If however, the data signal captured is necessary for a later stage of the semiconductor device, then an internal data transfer blocking circuit blocks the data signal from being latched in the latch circuit, while the clock transfer blocking circuit and the external data transfer blocking circuit cause the captured clock signal and data signal to be output to the data output circuit.
REFERENCES:
patent: 6456271 (2002-09-01), Tamai et al.
patent: 6697040 (2004-02-01), Imajo et al.
patent: 2001/0048415 (2001-12-01), Morii
patent: 2004/0046727 (2004-03-01), Fujioka et al.
Kumagai Masao
Udo Shinya
Arent & Fox PLLC
Tran Henry N.
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