Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
2001-06-06
2004-10-05
Hjerpe, Richard (Department: 2674)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S092000
Reexamination Certificate
active
06801176
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a liquid crystal display that comprises the semiconductor device.
2. Description of the Related Art
The structure of a conventional liquid crystal display having a thin film transistor (poly-Si TFT (Thin Film Transistor)) formed of polycrystalline silicon is shown in FIG.
14
. Pixels each of which comprises a poly-Si
132
and a pixel capacitance
131
are disposed in matrix-fashion on the pixel region
124
, and the gate of each poly-Si TFT
132
is connected to a gate line
134
and the drain is connected to a signal line
133
. Only one pixel is shown in
FIG. 14
for the purpose of simplification of the drawing herein. A gate line driving buffer
127
is disposed at the end of the gate line
134
, and the gate line driving buffer
127
is scanned by means of a gate line shift register
126
. The gate line shift register
126
is driven by means of a gate line clock generator
125
. A signal line selection switch
123
is disposed at the end of the signal line
133
, and the signal line selection switch
123
is scanned by means of a shift register
122
. The signal line shift register
122
is driven by means of the signal line clock generator
121
. An analog signal input line is connected to the signal line selection switch
123
.
Next, the operation of
FIG. 14
will be described. The gate line shift register
126
selects the gate line successively through the gate line driving buffer
127
according to the clock pulse supplied from the gate line clock generator
125
. The poly-Si TFT
132
of the pixel on the selected row is set to be ON. The signal line shift register
122
scans the signal line selection switch
123
successively according to the clock pulse generated by means of the signal line clock generator
121
in the time period. The signal line selection switch
123
connects the corresponding signal line
133
to the analog signal input line
135
during scanning. Therefore, the image signal supplied to the analog signal input line
135
is written successively in the pixel capacitance
131
through the signal line
133
and the poly-Si TFT
132
.
Next, the basic circuit structure of the signal line clock generator
121
is shown in FIG.
15
. Each of inverters
101
to
105
and
111
to
115
comprises a CMOS circuit of poly-Si TFT. The input clock Vin is converted to the output clock &phgr; and &phgr;(inv.) having the phase that is inverted just by angle of &pgr; through the inverter circuits. Herein, &phgr;(inv.) means the waveform of inverted phase ideally. Because the output clock &phgr; and &phgr;(inv.) are involved in driving of one unit signal selection switch
123
in the form of pair through the signal line sift register
122
, it is important that the phase difference between both phases is equalized to &pgr; in order to improve the image quality. For example, IDRC (International Display Research Conference) 1994 Proceedings of Technical Paper, pp. 418 to 421 describes the prior art in detail.
The above-mentioned prior art describes the method for eliminating the error of the phase difference between the output clock &phgr; and &phgr;(inv.) of the same pair, but does not describe a method for eliminating the phase deviation between the output clock &phgr;
1
and &phgr;
2
of the different adjacent pair. If the phase deviates between both output clocks each other, when the signal selection switch
123
is turned on or turned off, the scan signal of the signal line selection switch
123
jumps from a signal selection switch
123
into the adjacent signal selection switch
123
, and the jump cause a problem. In detail, when the second signal selection switch
123
that is located adjacent to the first signal selection switch
123
is turned on before the first signal selection switch
123
that is ON currently is turned off, the scan signal of the second signal selection switch
123
jumps into the first signal selection switch
123
. Thereafter, when the first signal selection switch
123
is turned off, the scan signal of the first signal selection switch
123
jumps into the second signal selection switch
123
. As the result, the image quality becomes poor.
The above-mentioned problem is described in detail with reference to FIG.
16
and FIG.
17
.
FIG. 16
shows the input/output characteristic of the inverters
103
and
113
shown in FIG.
15
. &phgr;
1
shows the characteristic curve of the inverter
113
, and &phgr;
2
shows the characteristic curve of the inverter
103
. The logical threshold value of &phgr;
1
is Vth
1
and that of &phgr;
2
is Vth
2
, and &Dgr;Vth denotes the deviation between both threshold values. The deviation is mainly due to the local dispersion of the threshold value of pMOS and nMOS that are components of the CMOS circuit, and the &Dgr;Vth is particularly remarkable for the CMOS circuit having poly-Si TFT. Generally, the threshold value dispersion of the single crystal Si-MOS transistor ranges approximately from 20 to 30 mV, on the other hand the threshold value dispersion of the poly-Si TFT ranges from several hundreds mV to several V. The reason why the threshold value dispersion of the poly-Si TFT is larger than that of the single crystal Si-MOS transistor in principle is that poly-Si TFT contains grain boundaries.
Next, the time t dependency of the input clock Vin on the inverter is shown in FIG.
17
. The input clock Vin goes up from the low level voltage L to the high level voltage H step-wise with time. The deviation &Dgr;Vth between Vth
1
and Vth
2
corresponds to the difference &Dgr;t between t
1
and t
2
on the time axis, and &Dgr;t represents the logical inversion time deviation between the inverter
113
and the inverter
103
. For example, it is assumed that &Dgr;Vth is 1 V and the inclination of the step of Vin is 10
7
V/s, then &Dgr;t of 0.1&mgr; second is given. The time period of 0.1&mgr; second is sufficient for the scan signal to jump from a signal selection switch
123
into the adjacent signal selection switch
123
.
The dispersion of the logical threshold value of the inverter as described herein above causes the low driving voltage of the logic circuit such as poly-Si TFT circuit and is resultantly problematic in high speed operation.
SUMMARY OF THE INVENTION
It is an object of the present invention to reduce the adverse effect of the logical threshold value dispersion of the inversion logical circuit such as inverter in a semiconductor device.
The above-mentioned object is achieved by applying a method, in which in addition to the conventionally used binary logical input voltage served as the input voltage an additional DC input voltage that is set to a value between the high voltage and the low voltage of the binary logical input voltage is provided, an additional changeover means for switching between these voltages and an additional capacitance having one end connected to the output terminal of the changeover means are provided, the other end of the capacitance is connected to the input terminal of the binary inversion logical circuit, an additional switching means for holding the voltage constant while the connection between the input terminal and the output terminal of the binary inversion logical circuit is being ON is provided, and the switching means and the changeover means are set so that the switching means is turned off simultaneously at the time when or before the changeover means is switched to the binary logical input voltage.
The operation of the logical circuit is described hereinunder. When the switching means is turned on, a DC input voltage, namely the logical threshold value, is applied on the series connection of the capacitance and the binary inversion logical circuit to thereby reset the series connection. Next, while the binary logical input voltage is being applied with the switching means OFF, when the value becomes a DC input voltage, namely the logical threshold value, the binary inversion logical circuit starts the operation such as ON/OFF op
Antonelli Terry Stout & Kraus LLP
Hitachi , Ltd.
Hjerpe Richard
Laneau Ronald
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