Semiconductor device and layout method thereof

Details Semiconductor device and layout method thereof Semiconductor device and layout method thereof

2009-02-04

2011-11-08

Tran, Tan N (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Gate arrays

With particular signal path connections

C257S208000, C257S296000, C257SE29166

Reexamination Certificate

active

08053813

ABSTRACT:
A semiconductor device includes first lines extending in a first direction and formed in a first wiring layer in a predetermined arrangement order, second lines formed in a second wiring layer different from the first wring layer in the predetermined arrangement order, and contacts electrically connecting between the first lines and the second lines so as to match the arrangement order. In the semiconductor device, at least adjacent two tracks are defined in a linear manner parallel to a second direction perpendicular to the first direction. Then, each of the second lines includes a first line portion extending along one of the two tracks, a second line portion extending along another of the two tracks, and a connection portion connecting between the first and second line portions, while two or more of the contacts are formed at the connection portion.

REFERENCES:
patent: 6680501 (2004-01-01), Ito et al.
patent: 7109585 (2006-09-01), Kang et al.
patent: 2006/0011993 (2006-01-01), Kang et al.
patent: 10-125775 (1998-05-01), None
patent: 2006-32944 (2006-02-01), None

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