Semiconductor device and its manufacturing method

Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Including high voltage or high power devices isolated from...

Reexamination Certificate

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C257S510000, C257S506000, C257SE21206, C257SE21546

Reexamination Certificate

active

07439602

ABSTRACT:
A semiconductor device including memory cells isolated by a trench that may be self aligned with a stacked film pattern (7) has been disclosed. The memory cells may be flash memory cells having an active gate film (2) that may be thinner than a gate oxide film (30). The active gate film (2) may be located in a central portion under of a gate electrode (3). The gate oxide film (30) may be located under end portions of the gate electrode (3). In this way, a distance between a shoulder portion of a trench (11) and a gate electrode (3) may be increased. Thus, an electric field concentration in the shoulder portion of the trench (11) may be decreased and memory cell characteristics may be improved.

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patent: 5731221 (1998-03-01), Kwon
patent: 5859459 (1999-01-01), Ikeda
patent: 6096604 (2000-08-01), Cha et al.
patent: 2001/0042894 (2001-11-01), Brigham et al.
patent: 2002/0055217 (2002-05-01), Kanamori
patent: 2002/0096704 (2002-07-01), Fukumoto et al.
patent: 62216268 (1987-09-01), None
U.S. Appl. No. 10/032,764, Kanamori.

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