Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Reexamination Certificate
1998-11-19
2002-05-28
Loke, Steven (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
C257S522000, C257S776000
Reexamination Certificate
active
06396146
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device and its manufacturing method, and more particularly to a multi-layer metal wiring technology.
Hitherto, in a semiconductor device having metal wiring of two or more layers, when the lower surface of the metal wiring layer is flattened by CMP (chemical mechanical polishing) technology, a dummy pattern is generally disposed for enhancement of its flatness.
FIG. 27
is a sectional view showing a constitution for disposing two-layer metal wiring on a semiconductor device. After forming a semiconductor element, an interlayer insulating film
6
, and the like on a silicon substrate
1
, the metal wiring layer of first layer is patterned by lithographic technology and reactive ion etching technology. As a result, a signal line pattern
2
and a dummy pattern
3
for enhancing the flatness in the subsequent CMP process are formed.
Consequently, after depositing an SiO
2
interlayer insulating film
4
by plasma CVD technology, the interlayer insulating film
4
is flattened by the CMP technology so that the metal pattern of the first layer may not be exposed. Same as in the first layer, next, the signal line pattern
5
is patterned by the lithographic technology and reactive ion etching technology. In this way, in the metal wiring layer of the first layer, a dummy pattern
3
is present besides the signal line
2
and power source wire actually used as wiring.
In such conventional constitution, by placing the dummy pattern for enhancing the flatness in CMP flattening process, a problem of increase of parasitic capacity between signal lines occurs. As the parasitic capacity between signal lines increases, not only the signal propagation speed is lowered, but also the noise resistance of the device drops. Besides, owing to the dummy pattern, the resistance to dust becomes weaker, and the signal lines are shorted, and probability of lowering of yield becomes higher. Still worse, since the dummy pattern is in an electrically floating state, simulation by circuit simulator is difficult, and the circuit design is very difficult.
BRIEF SUMMARY OF THE INVENTION
The present invention is devised to solve the aforementioned problems, and it is hence an object thereof to provide a semiconductor device manufactured by CMP flattening process not accompanied by increase of parasitic capacity between signal lines due to metal dummy pattern used for CMP flattening, shorting due to dust and the like, or complication of circuit design, and a method of manufacturing the same.
To achieve the aforementioned object, according to the present invention, after completion of flattening by CMP, a dummy pattern is selectively etched by anisotropic etching through holes opened at specific intervals, and the opened holes are filled with an insulating film, and a cavity is formed. By forming a cavity in the portion of the dummy pattern in this manner, it is intended to solve the problem of parasitic capacity and difficulty of circuit design.
That is, the semiconductor device of the present invention comprises wiring patterns and dummy patterns formed on a first insulating film, a second insulating film provided in a region on the first insulating film containing the wiring patterns and dummy patterns, having the surface flattened by CMP, and second wiring patterns disposed on the second insulating film, in which the dummy patterns are formed selectively in cavities.
A semiconductor device manufacturing method of the present invention comprises a step of forming plural wiring patterns and plural dummy patterns on the first insulating film, a step of depositing a second insulating film in a region on the first insulating film including the plural wiring patterns and dummy patterns, a step of flattening the surface of the second insulating film by using the CMP technology, a step of selectively providing opening holes in the second insulating film on the plural dummy patterns, a step of etching the dummy patterns through the opening holes, a step of depositing a third insulating film in a region on the second insulating film including the opening holes, and a step of forming second wiring patterns on the third insulating film.
Since the dummy patterns are selectively etched by the anisotropic etching after completion of flattening by CMP, cavities are formed in the dummy patterns. As a result, the parasitic capacity between the signal lines decreases, and complication of circuit design can be prevented.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.
REFERENCES:
patent: 5461003 (1995-10-01), Havemann et al.
patent: 5519250 (1996-05-01), Numata
patent: 5792706 (1998-08-01), Michael et al.
patent: 5835987 (1998-11-01), Givens
patent: 5861674 (1999-01-01), Ishikawa
patent: 5863832 (1999-01-01), Doyle et al.
patent: 6091130 (2000-07-01), Oyamatsu et al.
patent: 63-211739 (1988-09-01), None
patent: 10-189509 (1998-07-01), None
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