Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2000-12-27
2003-04-29
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S740000, C438S620000, C438S637000, C438S672000
Reexamination Certificate
active
06555481
ABSTRACT:
This application is based on Japanese Patent Application HEI 11-374722, filed on Dec. 28, 1999, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
a) Field of the Invention
The present invention relates to a semiconductor device and its manufacture, and more particularly to a semiconductor device with a multi-layer wiring structure and its manufacture method.
b) Description of the Related Art
Improvements on multi-layer conductive wires are being made along with higher integration of semiconductor integrated circuit devices. Self-aligned contact (SAC) techniques are also adopted to form a contact in a narrow area. There are strong requests for reduction of the manufacturing cost of semiconductor integrated circuit devices. In order to lower the manufacturing cost, it is effective to reduce the number of masks.
FIGS. 23A and 23B
show an example of the structure of a dynamic random access memory (DRAM) according to conventional techniques.
FIG. 23A
is a vertical cross sectional view taken along a direction parallel to a bit line, and
FIG. 23B
is a vertical cross sectional view taken along a direction perpendicular to the bit line.
A bit line
111
a
shown in FIG.
23
A and an insulated gate electrode (word line)
104
shown in
FIG. 23B
do not actually appear in these cross sectional views, but are hidden in the background regions. However, these bit line
111
a
and gate electrode
104
are drawn for purposes of easy understanding.
As shown in
FIG. 23A
, a shallow trench isolation (STI) region
102
of an oxide film is buried in the surface layer of a p-type region
101
of a semiconductor substrate. The STI region
102
defines or surrounds respective active regions. On the surface of the active region, a gate oxide film and a gate electrode layer are laminated and patterned to form a pair of gate electrode structures each constituted of a gate oxide film
104
a
and a gate electrode
104
b
. An etching stopper film of silicon nitride or the like may be formed covering the upper and side surfaces of the insulated gate electrode. By using the gate electrode
104
b
as a mask, n-type impurity ions are implanted into the exposed active region. As a result, a source/drain region
103
a
to be connected to the bit line is formed in the central area of the active region, and a pair of source/drain regions
103
b
to be connected to storage capacitors are formed on both sides of the gate electrodes. A first interlayer insulating film
105
of silicon oxide or the like is formed on the substrate surface, covering the gate electrode.
A resist pattern or the like is formed on the first interlayer insulating film
105
, and contact holes to the source/drain regions
103
a
and
103
b
are formed through the first interlayer insulating film
105
. Thereafter, conductive material such as polysilicon is deposited, and the conductive material on the first interlayer insulating film
105
is removed to leave lower plugs
107
and
108
only in the contact holes.
Thereafter, a second interlayer insulating film
109
a
of silicon oxide or the like is deposited on the first interlayer insulating film. A mask pattern is formed on the silicon oxide film
109
a
. A trench is formed through the silicon oxide film
109
a
in order to form, for example, a bit line. After this mask pattern is removed, another mask pattern is formed having an opening corresponding to a contact area in the bottom area of the trench. By using this other mask pattern, the second interlayer insulating film
109
a
is etched to form a bit line contact hole. A bit line contact
111
b
is formed in the bit line contact hole, and a bit line
111
a
is formed in the bit line trench. These contact
111
b
and bit line
111
a
may be made of the same material or different materials.
A third interlayer insulating film
109
b
is deposited covering the bit line
111
a
. If SAC techniques are to be incorporated, the upper and side surfaces of the bit line
111
a
are covered with an etch stopper film.
A resist layer is formed on the surface of the third interlayer insulating film
109
b
, and an opening is formed through the interlayer insulating films
109
a
and
109
b
in an area corresponding to the storage electrode lower plug
108
. This opening is buried with a storage capacitor contact
114
to form a surface electrically connected to the source/drain region
103
b
in the surface of the third interlayer insulating film
109
b.
Thereafter, an insulating film
113
of silicon oxide or the like is formed, and a portion of the insulating film
113
where a storage electrode is to be formed, is removed. A storage electrode
116
is deposited, and the storage electrode on the upper surface of the insulting film
113
is removed. The surface of the storage electrode is covered with a capacitor dielectric film
117
, and a plate electrode
118
is formed on the capacitor dielectric film
117
.
FIG. 23B
shows the cross sectional structure perpendicular to that shown in FIG.
23
A. The storage electrode contact
114
is formed between a pair of bit lines
111
a
. As shown in
FIG. 23A
, by limiting the area occupied by the storage electrode contact
114
, a parasitic capacitance between the storage electrode and bit line can be suppressed small.
However, the structure shown in
FIGS. 23A and 23B
requires two masks, one for forming the storage electrode
116
and the other for forming the storage electrode contact
114
.
FIGS. 24A and 24B
show the structure of DRAM whose storage electrode and its contact are formed by one mask.
FIG. 24A
is a cross sectional view taken along a direction parallel to a bit line
111
a
, and
FIG. 24B
is a cross sectional view taken along a direction perpendicular to the bit line
111
a
. As shown in
FIGS. 24A and 24B
, in this structure, the same cross sectional shape of a storage electrode
116
extends downward to form a storage electrode contact
114
. Therefore, the same mask can be used for forming the storage electrode and storage electrode contact, reducing the number of masks by one.
However, as shown in
FIG. 24A
, the storage electrode contact
114
extends in parallel to the bit lines
111
a
in a large area and a parasitic capacitance therebetween increases. If an insulating film
109
c
formed in contact with the side walls of the bit line
111
a
is made of material having a large dielectric constant, such as silicon nitride, the parasitic capacitance increases greatly. If the insulating film
109
c
is made of silicon oxide film, there is no etch selectivity so that electrical shortage is likely to be formed between the storage electrode contact and bit line.
A hole continuous in a depth direction and having different cross sectional shapes generally requires two masks. If such a hole is to be formed by using one mask, it is difficult to control the cross sectional shape of the hole. If the number of masks is increased, the manufacturing cost is difficult to be lowered, whereas if the number of masks is reduced, desired electric characteristics are difficult to be obtained.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a semiconductor device manufacture method capable of realizing desired electric characteristics by using a smaller number of masks.
It is another object of the present invention to provide a semiconductor device manufacture method capable of forming a hole having different cross sectional shapes in a depth direction by using a smaller number of masks.
It is another object of the present invention to provide a semiconductor device manufacture method capable of reducing a parasitic capacitance by using a smaller number of masks.
It is still another object of the present invention to provide a semiconductor device with a small parasitic capacitance capable of being manufactured with a smaller number of masks.
According to one aspect of the present invention, there is provided a semiconductor device, comprising a semiconductor substrate; a lower structure formed on the semiconductor substrat
Armstrong Westerman & Hattori, LLP
Estrada Michelle
Fourson George
Fujitsu Limited
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