Active solid-state devices (e.g. – transistors – solid-state diode – Thin active physical layer which is – Tunneling through region of reduced conductivity
Reexamination Certificate
2007-01-02
2007-01-02
Schillinger, Laura M. (Department: 2813)
Active solid-state devices (e.g., transistors, solid-state diode
Thin active physical layer which is
Tunneling through region of reduced conductivity
C257S030000, C257S038000, C257S039000
Reexamination Certificate
active
10707525
ABSTRACT:
In a logic area, impurities are doped into the gate electrode and the source/drain diffusion regions of a MIS transistor. Thereafter in a memory cell area, word lines are patterned, source/drain regions are formed, and contact holes are formed. Side wall spacers of the MIS transistor in the logic area are made of silicon oxide. A semiconductor device of logic-memory can be manufactured by a reduced number of manufacture processes while the transistor characteristics are stabilized and the fine patterns in the memory cell are ensured.
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Anezaki Toru
Ema Taiji
Taniguchi Toshio
Armstrong Kratz Quintos Hanson & Brooks, LLP
Fujitsu Limited
Schillinger Laura M.
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