Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Reexamination Certificate
2002-07-31
2004-08-17
Clark, S. V. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
C257S770000
Reexamination Certificate
active
06777811
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device having a copper wiring and its fabrication method.
As a semiconductor device is more highly integrated, the width of a wiring and the interval between wirings are decreased and resultantly the resistance of a wiring or the capacitance between wirings is increased. When the resistance or capacity increases, the speed for an electrical signal to pass through a wiring lowers and resultantly the operation speed of a semiconductor device is limited. To prevent the above phenomenon, a method for forming a low-resistance wiring by using a copper (Cu) film has been positively studied in recent years.
A conventional semiconductor device, specifically a semiconductor device having a wiring formed by a Cu film and its fabrication method are described below by referring to the accompanying drawings.
FIGS. 21
to
26
are sectional views showing steps of a conventional semiconductor-device fabrication method.
First, as-shown in
FIG. 21
, a first silicon-dioxide (SiO
2
) film
3
, a silicon nitride (Si
3
N
4
) film
4
, and a second SiO
2
film
5
are formed in order on a semiconductor substrate
1
provided with a lower-layer wiring
2
formed by a Cu film.
Then, as shown in
FIG. 22
, a via hole
6
reaching the lower-layer wiring
2
is formed on the first SiO
2
film
3
and the Si
3
N
4
film
4
and a wiring groove
7
connecting with the via hole
6
is formed on the second SiO
2
film
5
by alternately applying the lithography method and the dry etching method twice each. In this case, a Cu film constituting the lower-layer wiring
2
is exposed to the bottom of the via hole
6
while the surface of the Cu film is immediately oxidized by oxygen (O
2
) in the air. Thereby, copper oxide {CuOx(x>O)} layer
8
is formed on the portion of the lower-layer wiring
2
exposed to the via hole
6
.
Then, as shown in
FIG. 23
, the CuOx layer
8
and a part of a Cu film forming lower-layer wiring
2
is removed by the sputter-etching method using an inert gas. However, because the removed portion is small compared to the entire lower-layer wiring
2
, the removed portion is omitted from
FIG. 23
downward.
Then, as shown in
FIG. 24
, a titanium nitride (TiN) film
9
is formed on the second SiO
2
film
5
including insides of the via hole
6
and wiring groove
7
by the chemical vapor deposition method. Thereby, the TiN film
9
is formed on the portion of the lower-layer wiring
2
exposed to the via hole
6
(that is, on the bottom face of the via hole
6
), the wall surface of the via hole
6
, and the wall surface and bottom face of the wiring groove
7
respectively.
Then, as shown in
FIG. 25
, a first Cu film
10
is formed on the TiN film
9
by the physical vapor deposition method and then, a second Cu film
11
is formed on the first Cu film
10
by the plating method to embed the via hole
6
and the wiring groove
7
by the second Cu film
11
.
Finally, as shown in
FIG. 26
, the portions of the TiN film
9
, first Cu film
10
, and second Cu film
11
outside the wiring groove
7
are removed by the chemical-mechanical polishing method (CMP method). Thereby, an upper-layer wiring
12
is formed which is constituted by the TiN film
9
, first Cu film
10
, and second Cu film
11
embedded in the via hole
6
and wiring groove
7
.
In the case of the conventional semiconductor device shown in
FIG. 26
, the TiN film
9
functions as a barrier metal film for preventing diffusion of Cu atoms contained in the first Cu film
10
and second Cu film
11
.
However, the above-described prior art has the following problems.
FIGS. 27
to
30
are illustrations for explaining problems of the prior art. In
FIGS. 27
to
30
, members same as those of the conventional semiconductor device shown in
FIGS. 21
to
26
are provided with the same symbols and their description is omitted.
As shown in
FIG. 27
, the first problem of the prior art is that when operating a semiconductor device for a long time at a high temperature, the portion of the TiN film
9
nearby the lower-layer wiring
2
is oxidized and thereby, a high-resistance titanium oxide (TiO
2
) layer
13
is formed. When the TiO
2
layer
13
is formed, the connection resistance between the lower-layer wiring
2
and the upper-layer wiring
12
increases and thereby, the operation speed of the semiconductor device lowers. This phenomenon specifically occurs due to the following mechanism. That is, to form the via hole
6
or wiring groove
7
by the dry etching method, oxygen (O) atoms contained in the first SiO
2
film
3
or second SiO
2
film
5
are implanted into a Cu film constituting the lower-layer wiring
2
and resultantly, an oxygen-atom-containing layer
14
is formed in the lower-layer wiring
2
. The oxygen-atom-containing layer
14
is distributed in a range wider than the CuOx layer
8
shown in FIG.
22
. When operating a semiconductor device for a long time under the above state, oxygen atoms contained in the oxygen-atom-containing layer
14
move toward the upper-layer
12
and resultantly, the portion of the TiN film
9
nearby the lower-layer wiring
2
is oxidized and the TiO
2
layer
13
is formed.
Then, as shown in
FIG. 28
, the second problem of the prior art is that Cu atoms pass through the TiN film
9
and reaches the first SiO
2
film
3
and second SiO
2
film
5
when using a semiconductor device for a long time at a high temperature because the power for preventing diffusion of Cu atoms contained in the first Cu film
10
and second Cu film
11
by the TiN film
9
is not sufficient (arrow in
FIG. 28
shows diffusion direction of Cu atoms). Cu atoms reaching the first SiO
2
film
3
and second SiO
2
film
5
form mobile ions in the first SiO
2
film
3
and second SiO
2
film
5
and thereby, leak current increases between adjacent vias or wirings (that is upper-layer wiring
12
) and resultantly the semiconductor device malfunctions.
Then, the third problem of the prior art is that when removing the CuOx film
8
and a part of a Cu film constituting lower-layer wiring
2
by the sputter-etching method using an inert gas (refer to FIG.
23
), Cu atoms contained in the lower-layer wiring
2
are scattered and attach to the wall surface of the via hole
6
or wiring groove
7
and thereby, a Cu layer
15
is formed as shown in FIG.
29
. When the Cu layer
15
is formed on the wall surface of the via hole
6
or wiring groove
7
, many Cu atoms are diffused in the first SiO
2
film
3
and second SiO
2
film
5
and thereby, adjacent vias or wirings are unexpectedly electrically connected each other and resultantly the yield of semiconductor devices is extremely lowered.
Finally, the fourth problem of the prior art is that when removing the portions of the TiN film
9
, first Cu film
10
, and second Cu film
11
outside the wiring groove
7
by the CMP method (refer to FIGS.
25
and
26
), exfoliation (refer to the portion enclosed by the broken line in
FIG. 30
) occurs at the interface between the second SiO
2
film
5
and the TiN film
9
, as shown in FIG.
30
. When the TiN film
9
is exfoliated from the second SiO
2
film
5
, the first Cu film
10
and second Cu film
11
are also exfoliated from the second SiO
2
film
5
with moving of the polishing cloth and thereby, a laminated wiring structure formed on a semiconductor substrate
1
is broken and resultantly the yield of semiconductor devices is extremely lowered.
SUMMARY OF THE INVENTION
In view of the above mentioned, it is an object of the present invention to make it possible to prevent a semiconductor device from malfunctioning and fabricate semiconductor devices at a high yield, while embodying a wiring with low-resistance employing a Cu film.
To achieve the above object, a first semiconductor device of the present invention comprises a lower-layer wiring made of copper or a copper alloy and formed on a semiconductor substrate, an insulating film deposited on the lower-layer wiring and provided with a via hole reaching the lower
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