Electric lamp and discharge devices: systems – Plural power supplies – Plural cathode and/or anode load device
Reexamination Certificate
1999-05-20
2001-07-17
Wong, Don (Department: 2821)
Electric lamp and discharge devices: systems
Plural power supplies
Plural cathode and/or anode load device
C315S169300, C345S055000, C345S076000
Reexamination Certificate
active
06262540
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to semiconductor devices and image forming apparatus, and more particularly to a semiconductor device having a light-emitting element array adaptable for use as a light source in electronic equipment including but not limited to laser printers and laser display units plus optical communications systems as well as optical signal processing apparatus, along with an image formation apparatus using the semiconductor device.
2. Description of the Related Art
In image formation equipment such as laser printers or the like, in the case where a light-emitting element array with a plurality of light-emitting elements is employed as the light source for producing light according to respective pixels of an image to be formed, it is required that each light-emitting element be driven in a way independent of others; to this end, one typical prior known approach is to provide lead wires for electrically feeding respective light-emitting elements (referred to as “individual leads” hereinafter) on a one-per-element basis. Accordingly, in the case of a light-emitting element array constituted from n rows and m columns of light-emitting elements, i.e. n×m light-emitting elements, a great number of connection leads as many as n×m lines are required resulting in creation of a problem as to an increase in production cost while making it difficult to achieve higher integration density of light-emitting elements.
One approach to avoiding this problem has been described in Published Unexamined Japanese Patent Application (“PUJPA”) No. 61-31271, which teaches the use of a technique for employing an LED array light source to form a hard copy or “print” image of high density. As shown in
FIG. 11
, the LED array
29
is made up of LED elements laid out two-dimensionally which are associated with a mesh-like or “matrix” pattern of rows of parallel leads (referred to as “cathode leads” hereinafter)
3
and columns of leads (“anode leads”)
4
. These cathode leads
3
and anode leads
4
have certain terminate ends at which wire bonding pads
33
and
32
are provided for use in individually driving the LED elements.
Another related art technique is found in PUJPA No. 7-503104 (“JP-A-7-503104”), which suggests use of a lamination of vertical-cavity surface-emitting laser structures with a transistor structure to thereby form a matrix lead pattern associated with respective transistor elements in the transistor structure. Driving a given transistor element permits light production at a corresponding vertical-cavity surface-emitting laser element that is placed on the upper side or the lower side of the transistor being presently driven.
The related art techniques set forth in the Japanese documents JP-A-61-31271 and JP-A-7-503104 require the use of a reduced number (n+m) in total of leads for the light-emitting element array of a 2D matrix of n rows and m columns of light-emitting elements; thus, it becomes possible to greatly reduce the required number of connection leads when compared to the case of the individual lead connection stated above. As a single wire bonding is formed per lead for example, a decrease in number of connection leads would lead to a decrease in number of wire bonding and also to a decrease in channel number of driver circuitry for use in driving the light-emitting element array. This in turn makes it possible to reduce production costs of the entire of equipment that employs this light-emitting element array, and also to achieve high integration density of such light-emitting element array.
Unfortunately, the related art approaches as taught by the Japanese documents JP-A-61-31271 and JP-A-7-503104 cited above are encountered with a problem which follows. In case the light-emitting elements constituting the light-emitting element array are further increased in number and disposed with higher integration density while narrowing the interval between rows of light-emitting elements and/or between columns thereof, the layout pitch of such leads (anode leads and cathode leads) becomes narrower resulting in incapability of implementation of the intended wire bonding, which in turn makes it impossible to achieve electrical interconnection required. In other words, the minimum lead pitch enabling wire bonding or else limits the row distance and column distance of those light-emitting elements making up a light-emitting element array. This will be explained more practically below.
In currently available wire-bonding techniques the minimum allowable pitch is 80 &mgr;m, or more or less. Suppose that wire-bonding pads are arrayed in a staggered or “zigzag” pattern in which pads are arrayed in two parallel lines with each pad in one line opposing a midway between adjacent one of the pads forming the other line. If this is the case, even where the minimum pitch of wire-bonding pads in each line is set at approximately 80 &mgr;m, the minimum lead pitch can be reduced down to about 40 &mgr;m, which is half of the minimum pad pitch. However, even in this case, the minimum lead pitch stays as large as about 40 &mgr;m.
Alternatively, imagine that the required number of connection leads is relatively less. In this case, expanding those portions of leads near the wire bonding pads into a sector shape might enable enlargement of the wire-bonding pad pitch. However, if the required number of such leads increases beyond several hundreds, then this pad pitch enlargement approach will no longer work well. This can be said because an increase in pitch of wire-bonding pads would result in an excessive increase in size of a substrate used. In view of this, the minimum layout pitch of those light-emitting elements constituting a light-emitting element array of relatively high density has been typically limited to 40 mm, or more or less.
It has been discussed that the related art approaches stated above suffer from a problem that a light-emitting element array having multiple light-emitting elements is strictly required to set the pitch of its leads at a limited value that permits electrical connection by wire bonding or the like, which hardly allows the pitch to decrease below a prespecified value of several tens of &mgr;m. This is a serious bar to reduction of the row distance and column distance of respective light-emitting elements, which in turn makes it impossible, or at least greatly difficult, to manufacture the intended light-emitting element array with high integration density required.
SUMMARY OF THE INVENTION
The present invention has been made in order to avoid the problem above, and its objective is to provide a semiconductor device capable of forming a light-emitting element array with high integration density, along with an image formation apparatus using the semiconductor device.
To attain the foregoing object, a semiconductor device according to this invention comprises: a light-emitting element array including a plurality of light-emitting elements and being formed on a semiconductor substrate; a switching element array formed on said semiconductor substrate monolithically with said light-emitting element array, and including switching elements laid out in a matrix form and each having an input end, an output end and a control end with one of said input end and said output end connected to any one of said plurality of light-emitting elements; first connection means for connecting the control end of each of the plurality of switching elements disposed in the same column or the other of the input end and the output end thereof to a first external connection end different per said same column; and second connection means for connecting the control end of each of the plurality of switching elements disposed in the same column or one side of the other of the input end and the output end thereof not being connected to said first external connection end to a second external connection end different per said same row
According to the semiconductor device of the invention, switching elements e
Fuji 'Xerox Co., Ltd.
Oliff & Berridg,e PLC
Tran Thuy Vinh
Wong Don
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