Semiconductor device and fabrication process thereof

Details Semiconductor device and fabrication process thereof Semiconductor device and fabrication process thereof

2002-08-30

2004-03-16

Kielin, Erik J. (Department: 2813)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Having substrate registration feature

C438S311000, C438S427000, C438S700000

Reexamination Certificate

active

06706610

ABSTRACT:

TECHNICAL FIELD
The present invention generally relates to production of semiconductor devices and more particularly the process of fabricating a semiconductor device including the step of forming a groove-type device isolation structure (STI: shallow trench isolation) on a so-called SOI (silcon-on-insulator) substrate. Further, the present invention relates to a semiconductor device fabricated by such a process.
Various techniques are used in the semiconductor devices that are subjected to the demand of high-speed operation, for improving the operational speed. Device miniaturization based on scaling law is a representative example. In addition, there is a proposal of using a semiconductor substrate having a so-called SOI structure, in which buried insulation layer is formed under a semiconductor layer forming an active layer, so as to decrease the parasitic capacitance of the diffusion regions that are formed in the active layer.
Meanwhile, various alignment marks are used in such highly miniaturized high-speed semiconductor devices when patterning various layers. Especially the patterning of a gate electrode, which exerts a decisive influence on the operational speed of the semiconductor device, is conducted by using an ultra-high resolution exposure apparatus, such as an electron beam exposure apparatus, in the case of so-called sub-quarter micron semiconductor devices having a gate length of less than 0.25 &mgr;m. As patterning of other layers is carried out by using an optical exposure apparatus that provides a large throughput, there is a demand in such advanced, ultrafine semiconductor devices, to form an alignment mark detectable by an electron beam exposure apparatus in advance, so as to align the gate electrode pattern to be formed accurately at the time of patterning of the gate electrode.
BACKGROUND ART
FIGS. 1A-1I
show the process of forming a gate alignment mark in the fabrication process of a conventional ultrafine semiconductor device.
Referring to
FIG. 1A
, the ultrafine semiconductor device is formed on an SOI substrate
10
in which an SiO
2
buried insulation layer
11
B having a thickness of typically 400 nm and a single crystal Si active layer
11
C having a thickness of typically 500 nm are formed consecutively on a support substrate
11
A of Si, and the like. Thereby, formation of the gate alignment mark is conducted simultaneously to the formation of the device isolation structure of the STI (shallow trench isolation) structure.
More specifically, a device array region
10
A, in which the STI device isolation structure is formed, and an alignment mark forming region
10
B, in which the gate alignment marks are formed, are defined on the SOI substrate
10
in the process of FIG.
1
A. The device array region
10
A and the alignment mark forming region
10
B are covered by an SiO
2
film
12
having a thickness of about 10 nm and an SiN film
13
having a thickness of about 110 nm. For example, the SiO
2
film
12
may be formed by a hydrochloric acid oxidation process conducted at 900° C. On the other hand, a CVD process is used to form the SiN film
13
.
Next, a resist pattern
14
shown in
FIG. 1B
is formed on the structure of
FIG. 1A
in the process of
FIG. 1B
, and the SiN film
13
and the SiO
2
film
12
underneath the SiN film
13
are patterned while using the resist pattern
14
as a mask. With this, SiO
2
patterns
12
A and SiN patterns
13
A are formed on the Si active layer
11
C as shown in FIG.
1
C. Referring to
FIGS. 1B and 1C
, the SiN pattern
13
A includes patterns
13
a
that cover the device region of the semiconductor device in the device array region
10
A. Further, the SiN pattern
13
A includes mask openings
13
b
and
13
c
corresponding to the alignment marks to be formed in the alignment mark formation region
10
B. The mask openings
13
b
and
13
c
are formed in correspondence to the resist openings
14
A and
14
B of the resist pattern
14
.
Thus, in the step of
FIG. 1D
, device isolation grooves
11
a
are formed in the active layer
11
C in correspondence to the device array region
10
A by patterning the Si active layer
11
C by a dry etching process while using the SiN pattern
13
A as a hard mask. Simultaneously, alignment marks
11
b
are formed in the active layer
11
C of the alignment mark formation region
10
B in the form of grooves. It should be noted that the dry etching process is conducted, when forming the device isolation grooves
11
a
and the alignment marks
11
b,
until the buried SiO
2
insulation film
11
B is exposed. As a result of the patterning process, there are formed device regions
11
c
of Si in the device array region
10
A between a device isolation groove
11
a
and a next device isolation groove
11
a.
In the alignment mark formation region
10
B, on the other hand, Si regions
11
d
are formed between a pair of mutually adjacent grooves. It should be noted that the Si region
11
d
forms the alignment mark together with the grooves
11
b.
Next, in the step of
FIG. 1E
, an SiO
2
film
15
is deposited on the structure of
FIG. 1D
by a CVD process such that the SiO
2
film
15
covers the device region
11
c
or the Si region
11
d
with a thickness of about 700 nm. Further, in the step of
FIG. 1F
, the SiO
2
film
15
is polished by a CMP process while using the SiN pattern
13
A as a polishing stopper. Further, in the step of
FIG. 1G
, the SiN pattern
13
A and also the SiO
2
pattern
12
A underneath the SiN pattern
13
A are removed respectively by using a pyrolytic phosphoric acid and an HF etchant. In the step of
FIG. 1E
, the SiO
2
film
15
fills the grooves
11
a
and
11
b,
and as a result, there are formed device isolation insulation film patterns
15
A in the step of
FIG. 1G
in the device array region
10
A in correspondence to the device isolation grooves
11
a.
Thereby, it should be noted that a device region
11
c
is formed between a pair of neighboring device isolation film patterns
15
A. Also, in the alignment mark formation region
10
B, the SiO
2
patterns
15
B are formed in correspondence to the grooves
11
b,
such that SiO
2
patterns sandwich the Si pattern
11
d
laterally.
Next, in the step of
FIG. 1H
, a resist pattern
16
exposing the alignment mark formation region
10
B of
FIG. 1I
is formed such that the resist pattern
16
covers the structure of
FIG. 1G
, and the SiO
2
pattern
15
B is removed in the alignment mark formation region
10
B by a dry etching process that uses a CHF
3
/CF
4
mixed gas as an etching gas for example, while using the resist pattern
16
as a mask. By removing the resist pattern
16
, a structure in which the device regions
11
c
are separated from each other by the device isolation regions
15
A, is formed in the device array region
10
A. Also, an alignment mark having a planar form explained previously with reference to
FIG. 1C
is formed in the alignment mark formation region
10
B such that the alignment mark is formed of the Si patterns
11
d
and the grooves
11
e
formed adjacent to the Si patterns
11
d
in correspondence to the SiO
2
patterns
15
B. It should be noted that
FIG. 1H
is a cross-sectional diagram taken along a line x-x′ of FIG.
1
I.
In such a semiconductor device of the conventional construction, it should be noted that the gate electrode pattern is formed on the device region
11
c
in the array region
10
A by using a ultra high resolution exposure method including an electron beam exposure method as explained previously. Thereby, a Si pattern
11
d
in the alignment mark formation region
10
B is used as an alignment mark, and alignment of the exposure apparatus is achieved by detecting the step height associated with the Si pattern
11
d.
According to the conventional construction noted above, the formation of the alignment mark and the formation of the device isolation region are conducted simultaneously by using the same mask. Because of this, it is possible to form the gate electrode with high precision.
On the other hand, it is required that the Si patte

Affiliated with

Also associated with

Rating

Semiconductor device and fabrication process thereof does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor device and fabrication process thereof, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device and fabrication process thereof will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3200239