Semiconductor device and fabrication process therefor

Details Semiconductor device and fabrication process therefor Semiconductor device and fabrication process therefor

2000-09-18

2002-04-16

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Manufacture of electrical device controlled printhead

C438S425000

Reexamination Certificate

active

06372531

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a fabrication process therefor and particularly, to a semiconductor device having an isolation region and a fabrication process therefor.
2. Description of the Background Art
As an example of a conventional semiconductor device, photo diodes applied in IC for an optical pickup of a compact disc (CD) will be described. As shown in
FIGS. 25 and 27
, a plurality of photo diodes PD
11
to PD
14
are first formed on a p-type silicon substrate
101
. The photo diodes PD
11
to PD
14
are electrically isolated from one another by lower and upper isolation regions
103
and
105
, strip portions of each of which intersect with each other in a plane.
In a region where the photo diodes PD
11
to PD
14
are formed, an n-type epitaxial layer
104
is formed on the p-type silicon substrate
101
with an N
+
-type buried region
102
interposed therebetween. On the n-type epitaxial layer
104
, a p-type layer
106
is formed.
Electrons and holes are generated in a depletion layer expanded from the junction interface between the p-type layer
106
and the n-type epitaxial
104
. Electrons are migrated into the n-type epitaxial layer
104
under an electric field in the depletion layer, while holes are migrated into the p-type layer
106
, to thus produce a potential difference between the n-type epitaxial layer
104
and the p-type layer
106
.
Further, similar to the above described case, a potential difference is produced between the N
+
-type buried region
102
and the p-type silicon substrate
101
by electrons and holes generated in a depletion layer expanding from the junction interface between the N
+
-type buried region
102
and the p-type silicon substrate
101
. With such a potential difference, a photovoltage is produced. In such a way, a current generated in each of the photo diodes PD
11
to PD
14
is amplified by a predetermined circuit (not shown).
Then, of a fabrication process for the above described semiconductor device, especially a method, by which the lower and upper isolation regions
103
and
105
are formed, will be explained. First, in a predetermined region of the p-type silicon substrate
101
, a p-type impurity used for forming the lower isolation region
103
is implanted by an ion-implantation method, followed by a predetermined heat treatment.
Then, the n-type epitaxial layer
104
is formed on the p-type silicon substrate
101
. With such steps applied, as shown in
FIG. 28
, a region
103
a
to serve as a lower isolation region, is formed. Thereafter, a p-type impurity is ion-implanted on a surface of the n-type epitaxial layer
104
above the region
103
a
and a predetermined heat treatment is applied to produce a region
105
a
to serve as an upper isolation region
105
, as shown in FIG.
29
. Thereby, other transistors and so on, which are not shown in the figure, are formed on the p-type silicon substrate
101
to thus complete a semiconductor device having photo diodes.
However, in the above described fabrication process for a semiconductor device, there has been a problem described below. After the region
103
a
to serve as the lower isolation region
103
is formed, an impurity in the region
103
a
diffuses in all directions during a heat treatment to form the region
105
a
to serve as the upper isolation region
105
.
Further, after the region
105
a
is formed, heat treatments during formation of impurity regions of other transistors not shown diffuse impurities of the region
105
a
in all directions. As a result of such diffusion, as shown in
FIG. 25
, in a semiconductor device completed after predetermined heat treatments, the isolation region in a section around an intersection of strip portions of the lower isolation region
103
or the upper isolation region
105
expands in size compared with its original one because of diffusion from adjacent parts to the section around the intersection.
On the other hand, a spot diameter of a laser light beam with which the photo diodes PD
11
to PD
14
are illuminated is limited and has a intensity distribution as shown in
FIG. 26
for example. Electron-hole pairs generated by a laser light beam are in situ recombined since almost no depletion layer is formed in the isolation regions
103
and
105
.
For this reason, a laser light beam with which the isolation regions
103
and
105
are illuminated contributes to almost no generation of a photovoltage. As described above, in the section around an intersection of strip portions of the lower isolation region
103
or the upper isolation region
105
, the isolation region expands in size compared with its original one by heat treatments in a fabrication process.
At this time, when the isolation regions
103
and
105
are illuminated with a laser light beam such that illumination by a light beam spot A as shown in
FIG. 25
covers the sections around an intersection of strip portions of the isolation regions
103
and
105
, a light component contributing to generation of a photovoltage decreases and thereby, a problem arises since high accuracy information become hard to obtain by the photo diodes as an optical pickup device.
SUMMARY OF THE INVENTION
The present invention has been made in order to solve the above problems. It is an object of the present invention to provide a semiconductor device with a high photovoltage generation efficiency and it is another object of the present invention to provide a fabrication process for such a semiconductor device.
A first semiconductor device of an aspect of the present invention, including an isolation region having strip portions that intersect with each other in a plane, is provided with a first conductivity type semiconductor substrate, a second conductivity type layer and a first conductivity type layer. The second conductivity type layer is formed on the semiconductor substrate. The first conductivity type layer is formed on the second conductivity type layer. The isolation region is formed from a surface of the first conductivity type layer to a surface of the semiconductor substrate and partitions the first conductivity type and second conductivity type layers into a plurality of regions. Arms of strip portions of the isolation region are narrowed in width toward a center of an intersection of the strip portions in a section around the intersection.
According to the semiconductor device, since arms of strip portions of an isolation region are narrowed in width toward a center of an intersection of the strip portions in a section around the intersection, a depletion layer at the interface between the first and second conductivity type layers can expand more toward the intersection of the strip portions compared with a conventional semiconductor device. Further, similar to the above described case, a depletion layer at the interface between the semiconductor substrate and the second layer can expand more. With the expansion of the depletion layers, even when illumination with a laser light beam covers a section around an intersection of the strip portions, no electron-hole pairs generated in a depletion layer are in situ recombined under an electric field in the depletion layer expanding close to the section around the intersection, which can contribute to generation of photovoltage.
A second semiconductor device of an aspect of the present invention, including an isolation region having strip portions that intersect with each other in a plane, is provided with a first conductivity type semiconductor substrate, a second conductivity type layer and a first conductivity type layer. The second conductivity type layer is formed on the semiconductor substrate. The first conductivity type layer is formed on the second conductivity type layer. The isolation region includes lower and upper isolation regions and is formed from a surface of the first conductivity type layer to a surface of the semiconductor substrate and partitions the first conductivity type and second conductivit

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